From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=217.140.101.70; helo=foss.arm.com; envelope-from=marc.zyngier@arm.com; receiver=edk2-devel@lists.01.org Received: from foss.arm.com (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by ml01.01.org (Postfix) with ESMTP id 3F9EA224872AE for ; Tue, 13 Mar 2018 02:27:14 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F402A1596; Tue, 13 Mar 2018 02:33:35 -0700 (PDT) Received: from [10.1.207.62] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0BE2B3F487; Tue, 13 Mar 2018 02:33:34 -0700 (PDT) To: Heyi Guo , edk2-devel@lists.01.org Cc: Yi Li , Leif Lindholm , Ard Biesheuvel References: <1520901090-96694-1-git-send-email-heyi.guo@linaro.org> <1520901090-96694-2-git-send-email-heyi.guo@linaro.org> From: Marc Zyngier Organization: ARM Ltd Message-ID: <0403f2bf-d6a8-b101-73a2-949946f71e46@arm.com> Date: Tue, 13 Mar 2018 09:33:33 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <1520901090-96694-2-git-send-email-heyi.guo@linaro.org> Subject: Re: [PATCH v2 1/1] ArmPkg/TimerDxe: Add ISB for timer compare value reload X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Mar 2018 09:27:15 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 7bit On 13/03/18 00:31, Heyi Guo wrote: > If timer interrupt is level sensitive, reloading timer compare > register has a side effect of clearing GIC pending status, so a "ISB" > is needed to make sure this instruction is executed before enabling > CPU IRQ, or else we may get spurious timer interrupts. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Heyi Guo > Signed-off-by: Yi Li > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Cc: Marc Zyngier > --- > > Notes: > v2: > - Use ISB instead of DSB [Marc] > - Update commit message accordingly. > > ArmPkg/Drivers/TimerDxe/TimerDxe.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > index 33d7c922221f..32abee8726a0 100644 > --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c > +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c > @@ -337,6 +337,7 @@ TimerInterruptHandler ( > > // Set next compare value > ArmGenericTimerSetCompareVal (CompareValue); > + ArmInstructionSynchronizationBarrier (); > ArmGenericTimerEnableTimer (); > } Sorry for being pedantic here, but it would make more sense if ISB was placed after the enabling of the timer. Otherwise, you only force the update of the comparator. But on the other hand, the timer was never disabled the first place, in which case you'd wonder why you're trying to enable it again. So either you leave the ISB here and remove the enable call, or move the ISB after the enable. Thanks, M. -- Jazz is not dead. It just smells funny...