From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web09.588.1581052221402730407 for ; Thu, 06 Feb 2020 21:10:21 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: liming.gao@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Feb 2020 21:10:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,411,1574150400"; d="scan'208";a="226372403" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga008.fm.intel.com with ESMTP; 06 Feb 2020 21:10:20 -0800 Received: from shsmsx603.ccr.corp.intel.com (10.109.6.143) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 6 Feb 2020 21:10:16 -0800 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by SHSMSX603.ccr.corp.intel.com (10.109.6.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 7 Feb 2020 13:10:15 +0800 Received: from shsmsx606.ccr.corp.intel.com ([10.109.6.216]) by SHSMSX606.ccr.corp.intel.com ([10.109.6.216]) with mapi id 15.01.1713.004; Fri, 7 Feb 2020 13:10:15 +0800 From: "Liming Gao" To: Felix Polyudov , "devel@edk2.groups.io" CC: "Kinney, Michael D" , "manickavasakamk@ami.com" Subject: Re: [PATCH] MdePkg: Add PCI Express 5.0 Header File Thread-Topic: [PATCH] MdePkg: Add PCI Express 5.0 Header File Thread-Index: AQHV26JeasSAuP4Z6Eiyq9BnKLVYHKgPMgfw Date: Fri, 7 Feb 2020 05:10:15 +0000 Message-ID: <066f801dfccd49e5942241c51496d482@intel.com> References: <20200204213012.67268-1-felixp@ami.com> In-Reply-To: <20200204213012.67268-1-felixp@ami.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.2.0.6 dlp-product: dlpe-windows dlp-reaction: no-action x-originating-ip: [10.239.127.36] MIME-Version: 1.0 Return-Path: liming.gao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Felix: The patch is good. Is any test for the header file, such as build? Thanks Liming > -----Original Message----- > From: Felix Polyudov > Sent: Wednesday, February 5, 2020 5:30 AM > To: devel@edk2.groups.io > Cc: Kinney, Michael D ; Gao, Liming ; manickavasakamk@ami.com > Subject: [PATCH] MdePkg: Add PCI Express 5.0 Header File >=20 > The header includes Physical Layer PCI Express Extended Capability > definitions based on section 7.7.6 of PCI Express Base Specification 5.0. >=20 > Signed-off-by: Felix Polyudov > --- > MdePkg/Include/IndustryStandard/PciExpress50.h | 136 +++++++++++++++++++= ++++++ > 1 file changed, 136 insertions(+) > create mode 100644 MdePkg/Include/IndustryStandard/PciExpress50.h >=20 > diff --git a/MdePkg/Include/IndustryStandard/PciExpress50.h b/MdePkg/Incl= ude/IndustryStandard/PciExpress50.h > new file mode 100644 > index 0000000..26eae0b > --- /dev/null > +++ b/MdePkg/Include/IndustryStandard/PciExpress50.h > @@ -0,0 +1,136 @@ > +/** @file > +Support for the PCI Express 5.0 standard. > + > +This header file may not define all structures. Please extend as requir= ed. > + > +Copyright (c) 2020, American Megatrends International LLC. All rights re= served.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _PCIEXPRESS50_H_ > +#define _PCIEXPRESS50_H_ > + > +#include > + > +#pragma pack(1) > + > +/// The Physical Layer PCI Express Extended Capability definitions. > +/// > +/// Based on section 7.7.6 of PCI Express Base Specification 5.0. > +///@{ > +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_ID 0x002A > +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_32_0_VER1 0x1 > + > +// Register offsets from Physical Layer PCI-E Ext Cap Header > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES_OFFSET = 0x04 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL_OFFSET = 0x08 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS_OFFSET = 0x0C > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1_OFFSE= T 0x10 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2_OFFSE= T 0x14 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1_OFFS= ET 0x18 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2_OFFS= ET 0x1C > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL_OF= FSET 0x20 > + > +typedef union { > + struct { > + UINT32 EqualizationByPassToHighestRateSupport : 1; = // bit 0 > + UINT32 NoEqualizationNeededSupport : 1; = // bit 1 > + UINT32 Reserved1 : 6; = // Reserved bit 2:7 > + UINT32 ModifiedTSUsageMode0Support : 1; = // bit 8 > + UINT32 ModifiedTSUsageMode1Support : 1; = // bit 9 > + UINT32 ModifiedTSUsageMode2Support : 1; = // bit 10 > + UINT32 ModifiedTSReservedUsageModes : 5; = // bit 11:15 > + UINT32 Reserved2 : 16;= // Reserved bit 16:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES; > + > +typedef union { > + struct { > + UINT32 EqualizationByPassToHighestRateDisable : 1; = // bit 0 > + UINT32 NoEqualizationNeededDisable : 1; = // bit 1 > + UINT32 Reserved1 : 6; = // Reserved bit 2:7 > + UINT32 ModifiedTSUsageModeSelected : 3; = // bit 8:10 > + UINT32 Reserved2 : 21;= // Reserved bit 11:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL; > + > +typedef union { > + struct { > + UINT32 EqualizationComplete : 1; // bit 0 > + UINT32 EqualizationPhase1Success : 1; // bit 1 > + UINT32 EqualizationPhase2Success : 1; // bit 2 > + UINT32 EqualizationPhase3Success : 1; // bit 3 > + UINT32 LinkEqualizationRequest : 1; // bit 4 > + UINT32 ModifiedTSRcvd : 1; // bit 5 > + UINT32 RcvdEnhancedLinkControl : 2; // bit 6:7 > + UINT32 TransmitterPrecodingOn : 1; // bit 8 > + UINT32 TransmitterPrecodeRequest : 1; // bit 9 > + UINT32 NoEqualizationNeededRcvd : 1; // bit 10 > + UINT32 Reserved : 21; // Reserved bit 11:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS; > + > +typedef union { > + struct { > + UINT32 RcvdModifiedTSUsageMode : 3; // bit 0:2 > + UINT32 RcvdModifiedTSUsageInfo1 : 13; // bit 3:15 > + UINT32 RcvdModifiedTSVendorId : 16; // bit 16:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1; > + > +typedef union { > + struct { > + UINT32 RcvdModifiedTSUsageInfo2 : 24; // bit 0:23 > + UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25 > + UINT32 Reserved : 6; // Reserved bit 26:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2; > + > +typedef union { > + struct { > + UINT32 TransModifiedTSUsageMode : 3; // bit 0:2 > + UINT32 TransModifiedTSUsageInfo1 : 13; // bit 3:15 > + UINT32 TransModifiedTSVendorId : 16; // bit 16:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1; > + > +typedef union { > + struct { > + UINT32 TransModifiedTSUsageInfo2 : 24; // bit 0:23 > + UINT32 AltProtocolNegotiationStatus : 2; // bit 24:25 > + UINT32 Reserved : 6; // Reserved bit 26:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2; > + > +typedef union { > + struct { > + UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3 > + UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7 > + } Bits; > + UINT8 Uint8; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL; > + > +typedef struct { > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CAPABILITIES Capablit= ies; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_CONTROL Control; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_STATUS Status; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA1 RcvdModi= fiedTs1Data; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_RCVD_MODIFIED_TS_DATA2 RcvdModi= fiedTs2Data; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA1 TransMod= ifiedTs1Data; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_TRANS_MODIFIED_TS_DATA2 TransMod= ifiedTs2Data; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_32_0_LANE_EQUALIZATION_CONTROL LaneEqua= lizationControl[1]; > +} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_32_0; > +///@} > + > +#pragma pack() > + > +#endif > -- > 2.10.0.windows.1 >=20 >=20 > Please consider the environment before printing this email. >=20 > The information contained in this message may be confidential and proprie= tary to American Megatrends (AMI). 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