From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8BC821A1DF4 for ; Mon, 22 Aug 2016 04:28:31 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP; 22 Aug 2016 04:28:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,559,1464678000"; d="scan'208";a="751954867" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by FMSMGA003.fm.intel.com with ESMTP; 22 Aug 2016 04:28:31 -0700 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 22 Aug 2016 04:28:30 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 22 Aug 2016 04:28:29 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.147]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.8]) with mapi id 14.03.0248.002; Mon, 22 Aug 2016 19:28:27 +0800 From: "Shi, Steven" To: Ard Biesheuvel , "edk2-devel@lists.01.org" , "Gao, Liming" , "Zhu, Yonghong" Thread-Topic: [PATCH] BaseTools/GenFw: ignore dynamic RELA sections Thread-Index: AQHR/F4FfVeRvvFF7UmYhGl0ABct8aBU1HUg Date: Mon, 22 Aug 2016 11:28:27 +0000 Message-ID: <06C8AB66E78EE34A949939824ABE2B31033908B1@shsmsx102.ccr.corp.intel.com> References: <1471860861-32600-1-git-send-email-ard.biesheuvel@linaro.org> In-Reply-To: <1471860861-32600-1-git-send-email-ard.biesheuvel@linaro.org> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYTc1Nzk3NjAtZTE1NC00NzFkLWJhMTQtNjY4MjY1YzIxZTBjIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IjRqSU5kUk9DbTJ3YmNxV0tHcGNrZXFCTGN2Wnc0TGgwVkdsdEpqZVNMM3M9In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] BaseTools/GenFw: ignore dynamic RELA sections X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 22 Aug 2016 11:28:31 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Ard, I like you path, and it makes the code look more clear. But in fact, old co= de should already ignore the dynamic RELA sections implicitly.=20 Like below code, when the GenFw use .rela section info value, which is 0, t= o get .rela target applying section address in SecShdr, it will point to NU= LL section [0]. And the next section type checking, which is (*Filter)(SecS= hdr), will fails and then stop the .rela section relocation process. Line 685 of BaseTools\Source\C\GenFw\Elf64Convert.c=20 // // Relocation section found. Now extract section information that the = relocations // apply to in the ELF data and the new COFF data. // SecShdr =3D GetShdrByIndex(RelShdr->sh_info); SecOffset =3D mCoffSectionsOffset[RelShdr->sh_info]; // // Only process relocations for the current filter type. // if (RelShdr->sh_type =3D=3D SHT_RELA && (*Filter)(SecShdr)) { ... ... } But anyway, I still support you add this patch. Steven Shi Intel\SSG\STO\UEFI Firmware Tel: +86 021-61166522 iNet: 821-6522 > -----Original Message----- > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > Sent: Monday, August 22, 2016 6:14 PM > To: edk2-devel@lists.01.org; Gao, Liming ; Shi, > Steven ; Zhu, Yonghong > Cc: Ard Biesheuvel > Subject: [PATCH] BaseTools/GenFw: ignore dynamic RELA sections >=20 > When building PIE (ET_DYN) executables, an additional RELA section is > emitted (in addition to the per-section .rela.text and .rela.data section= s) > that is intended to be resolved at runtime by a ET_DYN compatible loader. >=20 > At the moment, due to the fact that we don't support GOT based relocation= s, > this dynamic RELA section only contains relocations that are redundant, > i.e., each R_xxx_RELATIVE relocation it contains duplicates a R_xxx_ABS64 > relocation appear in .rela.text or .rela.data, and so we can simply ignor= e > this section (and we already ignore it in practice due to the fact that i= t > points to the NULL section, which has the SHF_ALLOC bit cleared) >=20 > For example, >=20 > Section Headers: > [Nr] Name Type Address Offset > Size EntSize Flags Link Info Align > [ 0] NULL 0000000000000000 00000000 > 0000000000000000 0000000000000000 0 0 0 > [ 1] .text PROGBITS 0000000000000240 000000c0 > 000000000000427c 0000000000000008 AX 0 0 64 > [ 2] .rela.text RELA 0000000000000000 00009310 > 0000000000001bf0 0000000000000018 I 7 1 8 > [ 3] .data PROGBITS 00000000000044c0 00004340 > 00000000000046d0 0000000000000000 WA 0 0 64 > [ 4] .rela.data RELA 0000000000000000 0000af00 > 0000000000000600 0000000000000018 I 7 3 8 > [ 5] .rela RELA 0000000000008bc0 00008a10 > 0000000000000600 0000000000000018 0 0 8 > [ 6] .shstrtab STRTAB 0000000000000000 0000b500 > 0000000000000037 0000000000000000 0 0 1 > [ 7] .symtab SYMTAB 0000000000000000 00009010 > 0000000000000210 0000000000000018 8 17 8 > [ 8] .strtab STRTAB 0000000000000000 00009220 > 00000000000000eb 0000000000000000 0 0 1 >=20 > Relocation section '.rela.data' at offset 0xaf00 contains 64 entries: > Offset Info Type Sym. Value Sym. Name= + Addend > 000000004800 000100000001 R_X86_64_64 0000000000000240 .text + > 3f5b > 000000004808 000100000001 R_X86_64_64 0000000000000240 .text + > 3f63 > 000000004810 000100000001 R_X86_64_64 0000000000000240 .text + > 3f79 > 000000004818 000100000001 R_X86_64_64 0000000000000240 .text + > 3f90 > 000000004820 000100000001 R_X86_64_64 0000000000000240 .text + > 3fa6 > ... >=20 > Relocation section '.rela' at offset 0x8a10 contains 64 entries: > Offset Info Type Sym. Value Sym. Name= + Addend > 000000004800 000000000008 R_X86_64_RELATIVE 419b > 000000004808 000000000008 R_X86_64_RELATIVE 41a3 > 000000004810 000000000008 R_X86_64_RELATIVE 41b9 > 000000004818 000000000008 R_X86_64_RELATIVE 41d0 > 000000004820 000000000008 R_X86_64_RELATIVE 41e6 > 000000004828 000000000008 R_X86_64_RELATIVE 41ff > ... >=20 > Note that GOT based relocations result in entries that *only* appear in t= he > dynamic .rela section and not in .rela.text or .rela.data. This means two > things for supporting GOT based relocations: > - we should check that a dynamic RELA section exists > - we should filter out duplicates between .rela and .rela.xxx, to prevent > emitting duplicate fixups into the PE/COFF .reloc section. >=20 > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > --- > BaseTools/Source/C/GenFw/Elf64Convert.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) >=20 > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c > b/BaseTools/Source/C/GenFw/Elf64Convert.c > index 708c1a1d91a7..acf435712146 100644 > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > @@ -683,6 +683,20 @@ WriteSections64 ( > } >=20 > // > + // If this is a ET_DYN (PIE) executable, we will encounter a dynamic > SHT_RELA > + // section that applies to the entire binary, and which will have it= s section > + // index set to #0 (which is a NULL section with the SHF_ALLOC bit > cleared). > + // > + // In the absence of GOT based relocations (which we currently don't > support), > + // this RELA section will mostly contain R_xxx_RELATIVE relocations,= one > for > + // every R_xxx_ABS64 relocation appearing in the per-section RELA > sections. > + // (i.e., .rela.text and .rela.data) > + // > + if (RelShdr->sh_info =3D=3D 0) { > + continue; > + } > + > + // > // Relocation section found. Now extract section information that t= he > relocations > // apply to in the ELF data and the new COFF data. > // > -- > 2.7.4