From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BE06521DF8076 for ; Mon, 28 Aug 2017 08:28:54 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Aug 2017 08:31:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,442,1498546800"; d="scan'208,217";a="1188912768" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga001.fm.intel.com with ESMTP; 28 Aug 2017 08:31:33 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 28 Aug 2017 08:31:33 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.39]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.117]) with mapi id 14.03.0319.002; Mon, 28 Aug 2017 23:31:31 +0800 From: "Shi, Steven" To: Laszlo Ersek , edk2-devel-01 CC: "Kinney, Michael D" , "Gao, Liming" , Ard Biesheuvel Thread-Topic: [edk2] "practical" memory allocation limit? Thread-Index: AQHTH9m/B5z+I4nOkUmUdboLi0VXJaKZxkvw//+K8ACAAIjWoA== Date: Mon, 28 Aug 2017 15:31:30 +0000 Message-ID: <06C8AB66E78EE34A949939824ABE2B313B57610E@shsmsx102.ccr.corp.intel.com> References: <1714bf60-83a1-ce07-1d71-ac729d8e9dc8@redhat.com> <06C8AB66E78EE34A949939824ABE2B313B57604E@shsmsx102.ccr.corp.intel.com> <37998be6-89f9-23a7-b1f5-a4527651d708@redhat.com> In-Reply-To: <37998be6-89f9-23a7-b1f5-a4527651d708@redhat.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.22 Subject: Re: "practical" memory allocation limit? X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 15:28:55 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable OK, got it. Thanks. For the why the 64bits DXE usually prefer allocations below 4GB, there is a= good white paper elaborate the memory service initialization flows and can= explain the reason. Please see the page 23 in below white paper (I have ma= rk the answer in red). https://github.com/tianocore-docs/Docs/blob/master/White_Papers/A_Tour_Beyo= nd_BIOS_Securiy_Enhancement_to_Mitigate_Buffer_Overflow_in_UEFI.pdf Heap Management in EDK II In UEFI, the DxeCore maintains the heap usage. The UEFI driver or applicati= on may call AllocatePages/FreePages/AllocatePool/FreePool to allocate or free the resou= rce, or call GetMemoryMap() to review all of the memory usage. [Heap Initialization] When DxeIpl transfers control to the DxeCore, all of the resource informati= on is reported in a Hand-off-Block (HOB) [PI] list. The DxeCore constructs the heap based upon = the HOB information. See figure 4-2 Heap Initialization. 1) The DxeCore needs to find one region to serve as the initial memory in CoreInitializeMemoryServices() (https://github.com/tianocore/edk2/blob/master/MdeModulePkg/Core/Dxe/Gcd/G cd.c). The function is responsible for priming the memory map so that memor= y allocations and resource allocations can be made. If the memory region described by the= PHIT HOB is big enough to hold BIN and minimum initial memory, this memory region is us= ed as highest priority. It can make the memory BIN allocation to be at the same m= emory region with PHIT that has better compatibility to avoid memory fragmentation. Usua= lly the BIN size is already considered by platform PEIM when the platform PEIM calls InstallPeiMemory() to PEI core. Steven Shi Intel\SSG\STO\UEFI Firmware Tel: +86 021-61166522 iNet: 821-6522 > -----Original Message----- > From: Laszlo Ersek [mailto:lersek@redhat.com] > Sent: Monday, August 28, 2017 10:40 PM > To: Shi, Steven ; edk2-devel-01 devel@lists.01.org> > Cc: Kinney, Michael D ; Gao, Liming > ; Ard Biesheuvel > Subject: Re: [edk2] "practical" memory allocation limit? > > On 08/28/17 16:25, Shi, Steven wrote: > > Hi Laszlo, > > > > I happen to have a question about how to correctly get the system memor= y > size on Qemu. > > > > In the QemuInitializeRam() of OvmfPkg\PlatformPei\MemDetect.c, I add > debug info as below to trace the GetSystemMemorySizeBelow4gb() and > GetSystemMemorySizeAbove4gb() output. But the output results seems not > right if my input memory size > 4GB. See my commands and trace outputs in > below. > > > > > > > > MemDetect.c Line 602: > > > > // > > > > // Determine total memory size available > > > > // > > > > LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); > > > > UpperMemorySize =3D GetSystemMemorySizeAbove4gb (); > > > > DEBUG ((EFI_D_INFO, "LowerMemorySize=3D 0x%x\n", LowerMemorySize)); > > > > DEBUG ((EFI_D_INFO, "UpperMemorySize=3D 0x%x\n", UpperMemorySize)); > > > > > > > > My test commands and trace outputs: > > > > $ /opt/qemu/bin/qemu-system-x86_64 -m 5120 -enable-kvm -hda > /home/jshi19/workspace/simics5-project/images/luv- > v2.1_diskboot_gpt_x86_64_.img -machine pc-q35-2.9 -bios OVMF.fd -serial > file:serial.log > > > > LowerMemorySize=3D 0x80000000 //2GB, but should not it be 4GB? > > > > UpperMemorySize=3D 0xC0000000 //3GB, but should not it be 1GB? > > No, this is correct; the values returned are system memory *amounts*. > (On the QEMU command line, the "-m" switch says how much system > memory > you have, not the highest address in system memory.) > > In the 4GB address space, you don't have *just* system memory, you have > a whole bunch of MMIO too. (Most of that is used for 32-bit MMIO PCI BAR > allocation, some is used for the pflash chip range, LAPICs, etc.) On Q35 > you also have 256MB assigned to the MMCONFIG / ECAM area (which > provides > direct MMIO access to PCI config space for PCI 256 buses). > > The physical memory map also depends on the board model; on i440fx, the > 32-bit system memory can go up to 3GB, while on Q35, it only goes up to > 2GB. > > So, if you pass 5GB to a Q35 machine, 2GB of that are placed in the > address space at [0, 2G), and the other 3GB are placed in the address > space at [4G, 7G). > > > $ /opt/qemu/bin/qemu-system-x86_64 -m 6144 -enable-kvm -hda > /home/jshi19/workspace/simics5-project/images/luv- > v2.1_diskboot_gpt_x86_64_.img -machine pc-q35-2.9 -bios OVMF.fd -serial > file:serial.log > > > > LowerMemorySize=3D 0x80000000 //2GB, but should not it be 4GB? > > > > UpperMemorySize=3D 0x0 // 0GB, but should not it be 2GB= ? > > With 6G DRAM, 2G go low, and 4G go high. > > (Your output is misleading because you used the %x format specifier in > your debug message -- %Lx would be correct, for printing a UINT64 value.) > > Laszlo