From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=ray.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EB870211C2830 for ; Wed, 30 Jan 2019 22:53:36 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Jan 2019 22:53:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,543,1539673200"; d="scan'208";a="315103347" Received: from unknown (HELO [10.239.9.3]) ([10.239.9.3]) by fmsmga006.fm.intel.com with ESMTP; 30 Jan 2019 22:53:35 -0800 To: Digant H Solanki , "edk2-devel@lists.01.org" References: <20190131050028.12948-1-digant.h.solanki@intel.com> Cc: Liming Gao From: "Ni, Ray" Message-ID: <07527951-54fe-9563-72c9-e62f95c6dc08@Intel.com> Date: Thu, 31 Jan 2019 14:55:58 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.5.0 MIME-Version: 1.0 In-Reply-To: <20190131050028.12948-1-digant.h.solanki@intel.com> Subject: Re: [PATCH 2/2] IntelSiliconPkg\Include\IndustryStandard: Update IGD_OPREGION_MBOX3 Structure X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Jan 2019 06:53:37 -0000 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit On 1/31/2019 1:00 PM, Digant H Solanki wrote: > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1454 > Based on latest IGD OpRegion Spec, IGD_OPREGION_MBOX3 needs to be updated with two new members : Physical Address of Raw VBT Data (RVDA) and Size of Raw VBT Data (RVDS) > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Digant H Solanki > Cc: Liming Gao > Cc: Chaganty, Rangasai V > Cc: Ni, Ray > --- > IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h > index 5ce80a5be8..1c83efee40 100644 > --- a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h > +++ b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h > @@ -4,9 +4,7 @@ > > https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf > > - @note Fixed bug in the spec Mailbox3 - RM31 size from 0x45(69) to 0x46(70) > - > - Copyright (c) 2016, Intel Corporation. All rights reserved.
> + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the BSD License > which accompanies this distribution. The full text of the license may be found at > @@ -118,7 +116,9 @@ typedef struct { > UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for IFFS feature > UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer > UINT32 STAT; ///< Offset 0x3B6 State Indicator > - UINT8 RM31[0x46]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero. Bug in spec 0x45(69) > + UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. > + UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from Spec Version 0.90 to support VBT greater than 6KB. > + UINT8 RM31[0x3A]; ///< Offset 0x3C6 - 0x3FF Reserved Must be zero. > } IGD_OPREGION_MBOX3; > > /// > -- Thanks, Ray