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Received: from DM6PR12MB3163.namprd12.prod.outlook.com (20.179.71.154) by DM6PR12MB2764.namprd12.prod.outlook.com (20.176.116.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2686.29; Tue, 4 Feb 2020 23:02:28 +0000 Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::a0cd:463:f444:c270]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::a0cd:463:f444:c270%7]) with mapi id 15.20.2707.020; Tue, 4 Feb 2020 23:02:28 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [PATCH v4 25/40] OvmfPkg: Create a GHCB page for use during Sec phase Date: Tue, 4 Feb 2020 17:01:29 -0600 Message-Id: <08865bec872b03c80b2cabad58033c4facf35c9a.1580857303.git.thomas.lendacky@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: X-ClientProxiedBy: SN6PR16CA0062.namprd16.prod.outlook.com (2603:10b6:805:ca::39) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) Return-Path: thomas.lendacky@amd.com MIME-Version: 1.0 Received: from tlendack-t1.amd.com (165.204.77.1) by SN6PR16CA0062.namprd16.prod.outlook.com (2603:10b6:805:ca::39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2686.32 via Frontend Transport; Tue, 4 Feb 2020 23:02:27 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 8d684237-593e-43ac-db4f-08d7a9c64e98 X-MS-TrafficTypeDiagnostic: DM6PR12MB2764:|DM6PR12MB2764: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5516; X-Forefront-PRVS: 03030B9493 X-Forefront-Antispam-Report: SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(346002)(376002)(136003)(366004)(396003)(189003)(199004)(86362001)(54906003)(52116002)(7696005)(36756003)(6486002)(478600001)(6916009)(966005)(2906002)(186003)(16526019)(19627235002)(316002)(26005)(956004)(2616005)(8676002)(66476007)(66946007)(66556008)(81156014)(5660300002)(81166006)(4326008)(8936002);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR12MB2764;H:DM6PR12MB3163.namprd12.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;MX:1;A:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fC31whmzvAzT5a8yyxvuhpiOxBfmCZXbslfrnK41K3qQK4qeMlJESIFruE9OD4CrEuavlVGNz//MuYTU4j6F76P4dt3EYOdKg1/CelyXUuFRKxfn9PhZ8oS9wyYyO+dsYtAR2fswJGxiMYdHqqFg3n9cLXfBCcG08fqXOwz/qhDBeO4HCUAMOBLG9hFvsa6GPkC4ZI3KYHgcVRaqlJKhhvbsTciyQGBxMsNtJLySWpWfx5Vl3bt7+nqM+qfdCrfNBRrGd7NL8BCO0+b99PZzac4Ppj01Ps3g3Bhgtwk9Wx5UNZ7YRmh2n8mMXnpCWiQNuNsgk1GTVV3m3DNX3pELPOYcHm2SS3rer8yv7NMAaNx2EB8V8uJ912S3m0D1IEvYquQbjwAlpDNYASq7y/P+pbuEIoE5HiYjx8zIXauULiLY2xNzhqEs6QwVtqWfcGAT0MmkX3ztHzeDMq69MluHDvZLzilmI2nGlfpwX0qAA5BVF3i26tGQBuJuGjDvufLJcnLUuyVQ85rUTTK66gagTA== X-MS-Exchange-AntiSpam-MessageData: qYz3skyA57RNojtfh+fZ9mWQiQq+TUOiRnCwK7SX6bHwieAeh/qiM1hu3cF6iT9TYH4JG4jIzm/Xdygh3rpKH28eeNKECaZbp2j6sRTklEj44an6yXz5gnjqUTpn48OWzxG3epKv5wer23STo/8cHA== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8d684237-593e-43ac-db4f-08d7a9c64e98 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2020 23:02:28.6232 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0/iuHyrWp22qNsXiLJr1BwBDAufZhof5GvwIb+WyjFMluToWZ642jY07wXncWLIIT+fyZxmb3e8aKHHrOtu7NA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2764 Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198 A GHCB page is needed during the Sec phase, so this new page must be created. Since the #VC exception handler routines assume that a per-CPU variable area is immediately after the GHCB, this per-CPU variable area must also be created. Since the GHCB must be marked as an un-encrypted, or shared, page, an additional pagetable page is required to break down the 2MB region where the GHCB page lives into 4K pagetable entries. Create a new entry in the OVMF memory layout for the new page table page and for the SEC GHCB and per-CPU variable pages. After breaking down the 2MB page, update the GHCB page table entry to remove the encryption mask. The GHCB page will be used by the SEC #VC exception handler. The #VC exception handler will fill in the necessary fields of the GHCB and exit to the hypervisor using the VMGEXIT instruction. The hypervisor then accesses the GHCB in order to perform the requested function. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkg.dec | 5 ++ OvmfPkg/OvmfPkgX64.fdf | 6 ++ OvmfPkg/ResetVector/ResetVector.inf | 5 ++ OvmfPkg/ResetVector/Ia32/PageTables64.asm | 76 +++++++++++++++++++++++ OvmfPkg/ResetVector/ResetVector.nasmb | 17 +++++ 5 files changed, 109 insertions(+) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index d5fee805ef4a..19723786d729 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -228,6 +228,11 @@ [PcdsFixedAtBuild] ## Number of page frames to use for storing grant table entries. gUefiOvmfPkgTokenSpaceGuid.PcdXenGrantFrames|4|UINT32|0x33 + ## Specify the extra page table needed to mark the GHCB as unencrypted. + # The value should be a multiple of 4KB for each. + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase|0x0|UINT32|0x34 + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize|0x0|UINT32|0x35 + [PcdsDynamic, PcdsDynamicEx] gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10 diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf index 0488e5d95ffe..f541481dc95c 100644 --- a/OvmfPkg/OvmfPkgX64.fdf +++ b/OvmfPkg/OvmfPkgX64.fdf @@ -76,6 +76,12 @@ [FD.MEMFD] 0x007000|0x001000 gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize +0x008000|0x001000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize + +0x009000|0x002000 +gUefiCpuPkgTokenSpaceGuid.PcdSecGhcbBase|gUefiCpuPkgTokenSpaceGuid.PcdSecGhcbSize + 0x010000|0x010000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize diff --git a/OvmfPkg/ResetVector/ResetVector.inf b/OvmfPkg/ResetVector/ResetVector.inf index b0ddfa5832a2..9aedbe9b3640 100644 --- a/OvmfPkg/ResetVector/ResetVector.inf +++ b/OvmfPkg/ResetVector/ResetVector.inf @@ -26,6 +26,7 @@ [Sources] [Packages] OvmfPkg/OvmfPkg.dec MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec UefiCpuPkg/UefiCpuPkg.dec [BuildOptions] @@ -33,5 +34,9 @@ [BuildOptions] *_*_X64_NASMB_FLAGS = -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/ [Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdSecGhcbBase + gUefiCpuPkgTokenSpaceGuid.PcdSecGhcbSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize diff --git a/OvmfPkg/ResetVector/Ia32/PageTables64.asm b/OvmfPkg/ResetVector/Ia32/PageTables64.asm index abad009f20f5..9f86ddf6f08f 100644 --- a/OvmfPkg/ResetVector/Ia32/PageTables64.asm +++ b/OvmfPkg/ResetVector/Ia32/PageTables64.asm @@ -21,6 +21,11 @@ BITS 32 %define PAGE_2M_MBO 0x080 %define PAGE_2M_PAT 0x01000 +%define PAGE_4K_PDE_ATTR (PAGE_ACCESSED + \ + PAGE_DIRTY + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) + %define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \ PAGE_ACCESSED + \ PAGE_DIRTY + \ @@ -75,6 +80,37 @@ NoSev: SevExit: OneTimeCallRet CheckSevFeature +; Check if Secure Encrypted Virtualization - Encrypted State (SEV-ES) feature +; is enabled. +; +; Modified: EAX, EBX, ECX +; +; If SEV-ES is enabled then EAX will be non-zero. +; If SEV-ES is disabled then EAX will be zero. +; +CheckSevEsFeature: + xor eax, eax + + ; SEV-ES can't be enabled if SEV isn't, so first check the encryption + ; mask. + test edx, edx + jz NoSevEs + + ; Save current value of encryption mask + mov ebx, edx + + ; Check if SEV-ES is enabled + ; MSR_0xC0010131 - Bit 1 (SEV-ES enabled) + mov ecx, 0xc0010131 + rdmsr + and eax, 2 + + ; Restore encryption mask + mov edx, ebx + +NoSevEs: + OneTimeCallRet CheckSevEsFeature + ; ; Modified: EAX, EBX, ECX, EDX ; @@ -139,6 +175,46 @@ pageTableEntriesLoop: mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx loop pageTableEntriesLoop + OneTimeCall CheckSevEsFeature + test eax, eax + jz SetCr3 + + ; + ; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted. + ; This requires the 2MB page for this range be broken down into 512 4KB + ; pages. All will be marked encrypted, except for the GHCB. + ; + mov ecx, (GHCB_BASE >> 21) + mov eax, GHCB_PT_ADDR + PAGE_PDP_ATTR + mov [ecx * 8 + PT_ADDR (0x2000)], eax + + ; + ; Page Table Entries (512 * 4KB entries => 2MB) + ; + mov ecx, 512 +pageTableEntries4kLoop: + mov eax, ecx + dec eax + shl eax, 12 + add eax, GHCB_BASE & 0xFFE0_0000 + add eax, PAGE_4K_PDE_ATTR + mov [ecx * 8 + GHCB_PT_ADDR - 8], eax + mov [(ecx * 8 + GHCB_PT_ADDR - 8) + 4], edx + loop pageTableEntries4kLoop + + ; + ; Clear the encryption bit from the GHCB entry + ; + mov ecx, (GHCB_BASE & 0x1F_FFFF) >> 12 + mov [ecx * 8 + GHCB_PT_ADDR + 4], strict dword 0 + + mov ecx, GHCB_SIZE / 4 + xor eax, eax +clearGhcbMemoryLoop: + mov dword[ecx * 4 + GHCB_BASE - 4], eax + loop clearGhcbMemoryLoop + +SetCr3: ; ; Set CR3 now that the paging structures are available ; diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/ResetVector.nasmb index 75cfe16654b1..c25932513b80 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -53,8 +53,25 @@ %error "This implementation inherently depends on PcdOvmfSecPageTablesSize" %endif + %if (FixedPcdGet32 (PcdOvmfSecGhcbPageTableSize) != 0x1000) + %error "This implementation inherently depends on PcdOvmfSecGhcbPageTableSize" + %endif + + %if (FixedPcdGet32 (PcdSecGhcbSize) != 0x2000) + %error "This implementation inherently depends on PcdSecGhcbSize" + %endif + + %if ((FixedPcdGet32 (PcdSecGhcbBase) >> 21) != \ + ((FixedPcdGet32 (PcdSecGhcbBase) + FixedPcdGet32 (PcdSecGhcbSize) - 1) >> 21)) + %error "This implementation inherently depends on PcdSecGhcbBase not straddling a 2MB boundary" + %endif + %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset)) %include "Ia32/Flat32ToFlat64.asm" + + %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase)) + %define GHCB_BASE (FixedPcdGet32 (PcdSecGhcbBase)) + %define GHCB_SIZE (FixedPcdGet32 (PcdSecGhcbSize)) %include "Ia32/PageTables64.asm" %endif -- 2.17.1