From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@amazon.com header.s=amazon201209 header.b=uC2Oa4jA; spf=pass (domain: amazon.com, ip: 207.171.184.25, mailfrom: prvs=08806d5e6=graf@amazon.com) Received: from smtp-fw-9101.amazon.com (smtp-fw-9101.amazon.com [207.171.184.25]) by groups.io with SMTP; Thu, 11 Jul 2019 11:09:57 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amazon.com; i=@amazon.com; q=dns/txt; s=amazon201209; t=1562868597; x=1594404597; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=QM9gHfvg867m82YRopjWX5apQgXAQBgJgjBv87OHviU=; b=uC2Oa4jAYaqBaTE82HR/ZLV7YN8HTpGvLjnEU9rqAaWyTK8/aWpAXOV1 IEOssjI8u2e24ueoFHO5QDIJkH7d27gkNwqAF3YdQWNRybuLjnWutRiyQ PYS9pYiYz/mm4kGHdRPUtSyHlry4QIeoOy2Gw8EApsan+b30KscMLRT2y Y=; X-IronPort-AV: E=Sophos;i="5.62,479,1554768000"; d="scan'208";a="815688930" Received: from sea3-co-svc-lb6-vlan2.sea.amazon.com (HELO email-inbound-relay-1e-62350142.us-east-1.amazon.com) ([10.47.22.34]) by smtp-border-fw-out-9101.sea19.amazon.com with ESMTP; 11 Jul 2019 18:09:53 +0000 Received: from EX13MTAUWC001.ant.amazon.com (iad55-ws-svc-p15-lb9-vlan3.iad.amazon.com [10.40.159.166]) by email-inbound-relay-1e-62350142.us-east-1.amazon.com (Postfix) with ESMTPS id 7442DA24FD; Thu, 11 Jul 2019 18:09:52 +0000 (UTC) Received: from EX13D20UWC004.ant.amazon.com (10.43.162.41) by EX13MTAUWC001.ant.amazon.com (10.43.162.135) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 11 Jul 2019 18:09:51 +0000 Received: from EX13D20UWC001.ant.amazon.com (10.43.162.244) by EX13D20UWC004.ant.amazon.com (10.43.162.41) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Thu, 11 Jul 2019 18:09:50 +0000 Received: from EX13D20UWC001.ant.amazon.com ([10.43.162.244]) by EX13D20UWC001.ant.amazon.com ([10.43.162.244]) with mapi id 15.00.1367.000; Thu, 11 Jul 2019 18:09:50 +0000 From: "Alexander Graf" To: "devel@edk2.groups.io" , "lersek@redhat.com" CC: "leif.lindholm@linaro.org" Subject: Re: [edk2-devel] [PATCH] PL031: Actually disable interrupts Thread-Topic: [edk2-devel] [PATCH] PL031: Actually disable interrupts Thread-Index: AQHVN0LMlPGVTjd0iUaRFgASaq/8eabFp1uAgAARySQ= Date: Thu, 11 Jul 2019 18:09:50 +0000 Message-ID: <090D54B6-9EEF-4E9F-95A8-29C0342084DE@amazon.com> References: <20190710145311.12184-1-graf@amazon.com> <20190710171331.aj2smigjmtok4buz@bivouac.eciton.net>,<7df479df-21b9-b90d-3830-4035756289b6@redhat.com> In-Reply-To: <7df479df-21b9-b90d-3830-4035756289b6@redhat.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted MIME-Version: 1.0 Content-Language: de-DE Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > Am 11.07.2019 um 19:07 schrieb Laszlo Ersek : >=20 >> On 07/10/19 19:13, Leif Lindholm wrote: >>> On Wed, Jul 10, 2019 at 04:53:11PM +0200, Alexander Graf via Groups.Io = wrote: >>> The PL031 interrupt mask register (IMSC) is not very clearly documented >>> in the PL031 specification. However, bit 0 (RTCIMSC) indicates whether >>> interrupts are enabled, not disabled. >>=20 >> 3.3.5. Interrupt Mask Set or Clear register, RTCIMSC >> ... Writing 1 sets the mask. ... >>=20 >> 3.6. Interrupts >> ... This interrupt is enabled or disabled by changing the mask bit in >> RTCIMSC. To enable the interrupt, set bit[0] HIGH. ... >>=20 >> *boggle* >=20 > Heh :) >=20 > Alex, out of interest, what were the symptoms of this issue on your end? > Spurious interrupt confusing the firmware's exception handler, perhaps? No symptoms that I've encountered. I just stumbled over it while studying t= he device and its respective UEFI code :). But yes, you would see a spurious interrupt once the RTC wraps around to 0,= so in 2038. Not that that would matter, as by that time you lost the only = wall clock reference available on your ARM system anyway :). Alex