From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9060E1A1E56 for ; Tue, 13 Sep 2016 19:56:38 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP; 13 Sep 2016 19:56:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.30,332,1470726000"; d="scan'208";a="8049915" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga005.fm.intel.com with ESMTP; 13 Sep 2016 19:56:38 -0700 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 13 Sep 2016 19:56:37 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 13 Sep 2016 19:56:37 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.109]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.174]) with mapi id 14.03.0248.002; Wed, 14 Sep 2016 10:56:35 +0800 From: "Zeng, Star" To: "Tian, Feng" CC: "edk2-devel@lists.01.org" Thread-Topic: [patch] MdeModulePkg/XhciPei: 1ms delay before accessing MMIO reg in reset Thread-Index: AQHSDipAz0Boc2ytoUObHcJLTd5draB4Sr1Q Date: Wed, 14 Sep 2016 02:56:35 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB048310394BAD5C@shsmsx102.ccr.corp.intel.com> References: In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [patch] MdeModulePkg/XhciPei: 1ms delay before accessing MMIO reg in reset X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Sep 2016 02:56:38 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Star Zeng -----Original Message----- From: Tian, Feng=20 Sent: Wednesday, September 14, 2016 9:49 AM To: Zeng, Star Cc: edk2-devel@lists.01.org Subject: [patch] MdeModulePkg/XhciPei: 1ms delay before accessing MMIO reg = in reset Some XHCI HCs require to have 1ms delay before accessing any MMIO register = in reset. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian --- MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c | 1 + 1 file changed, 1 insertion(+) diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c b/MdeModulePkg/Bus/Pci/= XhciPei/XhcPeim.c index a58739f..cd5c5cd 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c @@ -407,6 +407,7 @@ XhcPeiResetHC ( } =20 XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET); + MicroSecondDelay (1000); Status =3D XhcPeiWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET,= FALSE, Timeout); ON_EXIT: DEBUG ((EFI_D_INFO, "XhcPeiResetHC: %r\n", Status)); -- 2.7.1.windows.2