From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8193C81EA7 for ; Tue, 22 Nov 2016 23:18:27 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga101.jf.intel.com with ESMTP; 22 Nov 2016 23:18:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,684,1473145200"; d="scan'208";a="1063149063" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga001.jf.intel.com with ESMTP; 22 Nov 2016 23:18:27 -0800 Received: from fmsmsx156.amr.corp.intel.com (10.18.116.74) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 22 Nov 2016 23:18:26 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx156.amr.corp.intel.com (10.18.116.74) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 22 Nov 2016 23:18:26 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.239]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.138]) with mapi id 14.03.0248.002; Wed, 23 Nov 2016 15:18:06 +0800 From: "Zeng, Star" To: "Tian, Feng" , "edk2-devel@lists.01.org" CC: Baraneedharan Anbazhagan , "Zeng, Star" Thread-Topic: [edk2] [patch] MdeModulePkg/Xhci: Add 10ms delay before sending SendAddr cmd to dev Thread-Index: AQHSRS0Y59EPF18BBUGG01HxyD2LbKDmKQSQ Date: Wed, 23 Nov 2016 07:18:06 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB048310395B9835@shsmsx102.ccr.corp.intel.com> References: In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_IC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTFkNmIwNGYtMmYwZC00NmI4LWIzN2MtZWQ0OGRmMTVlODkzIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6ImNjNjJwaE1OYTBUTzE4WTFQK3Y1WUloQVNNSjk4SXRERXFpMEJvTGRnVE09In0= x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [patch] MdeModulePkg/Xhci: Add 10ms delay before sending SendAddr cmd to dev X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Nov 2016 07:18:27 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Star Zeng -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Feng= Tian Sent: Wednesday, November 23, 2016 9:58 AM To: edk2-devel@lists.01.org Cc: Baraneedharan Anbazhagan ; Zeng, Star Subject: [edk2] [patch] MdeModulePkg/Xhci: Add 10ms delay before sending Se= ndAddr cmd to dev We send ADDRESS DEVICE CMD in XhcInitializeDeviceSlot(), which will cause X= HC issue a USB SET_ADDRESS request to the USB Device. According to USB spec, there should have a 10ms delay before this operation= after resetting a given port. But in original code, there is a possible path which may have no such 10ms = delay: UsbHubResetPort()->UsbHubSetPortFeature()->Stall(20)->UsbHubGetPortSt atus()->XhcPollPortStatusChange()->(if RESET_C bit is set)-> XhcInitializeD= eviceSlot()->(if RESET_C bit is set)->Stall(10) So this patch is used to fix above issue. Cc: Star Zeng Cc: Baraneedharan Anbazhagan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian Tested-by: Baraneedharan Anbazhagan --- MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h | 7 ++++++- MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 10 +++++++++- MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h | 8 +++++++- MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 10 +++++++++- 4 files changed, 31 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h b/MdeModulePkg/Bus/Pci/Xhc= iDxe/Xhci.h index 06cc73c..28e2402 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.h @@ -2,7 +2,7 @@ =20 Provides some data structure definitions used by the XHCI host controlle= r driver. =20 -Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -61,6 +61,11 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT; // #define XHC_RESET_TIMEOUT (1000) // +// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5. +// The unit is microsecond, setting it as 10ms. +// +#define XHC_RESET_RECOVERY_DELAY (10 * 1000) +// // XHC async transfer timer interval, set by experience. // The unit is 100us, takes 1ms as interval. // diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pc= i/XhciDxe/XhciSched.c index e37f674..4bec76a 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -2,7 +2,7 @@ =20 XHCI transfer scheduling routines. =20 -Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -2115,6 +2= 115,10 @@ XhcInitializeDeviceSlot ( // 8) Issue an Address Device Command for the Device Slot, where the com= mand points to the Input // Context data structure described above. // + // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec=20 + chapter 7.1.7.5 before sending SetAddress() request // to device. + // + gBS->Stall (XHC_RESET_RECOVERY_DELAY); ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext= [SlotId].InputContext, sizeof (INPUT_CONTEXT)); CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); @@ -2321,6 +2325,10 @@ XhcInitializeDeviceSlot64 ( // 8) Issue an Address Device Command for the Device Slot, where the com= mand points to the Input // Context data structure described above. // + // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec=20 + chapter 7.1.7.5 before sending SetAddress() request // to device. + // + gBS->Stall (XHC_RESET_RECOVERY_DELAY); ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext= [SlotId].InputContext, sizeof (INPUT_CONTEXT_64)); CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h b/MdeModulePkg/Bus/Pci/= XhciPei/XhcPeim.h index ccf4dc2..99f0396 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h @@ -1,7 +1,7 @@ /** @file Private Header file for Usb Host Controller PEIM =20 -Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availab= le under the terms and conditions @@ -53,6 +53,12 @@ typedef struct _USB_DE= V_CONTEXT USB_DEV_CONTEXT; #define XHC_RESET_TIMEOUT (1000) =20 // +// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5. +// The unit is microsecond, setting it as 10ms. +// +#define XHC_RESET_RECOVERY_DELAY (10 * 1000) + +// // Wait for root port state stable. // #define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND) diff --git a= /MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciPei/Xh= ciSched.c index 7f554f5..7a63dab 100644 --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c @@ -2,7 +2,7 @@ PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPp= iGuid which is used to enable recovery function from USB Drivers. =20 -Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availab= le under the terms and conditions @@ -1195,6 +1195,10 @@ XhcPeiInitializeDe= viceSlot ( // 8) Issue an Address Device Command for the Device Slot, where the com= mand points to the Input // Context data structure described above. // + // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec=20 + chapter 7.1.7.5 before sending SetAddress() request // to device. + // + MicroSecondDelay (XHC_RESET_RECOVERY_DELAY); ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext= [SlotId].InputContext, sizeof (INPUT_CONTEXT)); CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); @@ -1402,6 +1406,10 @@ XhcPeiInitializeDeviceSlot64 ( // 8) Issue an Address Device Command for the Device Slot, where the com= mand points to the Input // Context data structure described above. // + // Delay 10ms to meet TRSTRCY delay requirement in usb 2.0 spec=20 + chapter 7.1.7.5 before sending SetAddress() request // to device. + // + MicroSecondDelay (XHC_RESET_RECOVERY_DELAY); ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc->UsbDevContext= [SlotId].InputContext, sizeof (INPUT_CONTEXT_64)); CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); -- 2.7.1.windows.2 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel