From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 25B5781F5F for ; Fri, 10 Feb 2017 00:00:41 -0800 (PST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP; 10 Feb 2017 00:00:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,140,1484035200"; d="scan'208";a="819221340" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by FMSMGA003.fm.intel.com with ESMTP; 10 Feb 2017 00:00:40 -0800 Received: from fmsmsx116.amr.corp.intel.com (10.18.116.20) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 10 Feb 2017 00:00:40 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx116.amr.corp.intel.com (10.18.116.20) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 10 Feb 2017 00:00:40 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.177]) with mapi id 14.03.0248.002; Fri, 10 Feb 2017 16:00:37 +0800 From: "Zeng, Star" To: Leo Duran , "edk2-devel@ml01.01.org" CC: Laszlo Ersek , "Tian, Feng" , Brijesh Singh , "Zeng, Star" Thread-Topic: [edk2] [PATCH 1/3] MdeModulePkg: Add PCD PcdPteMemoryEncryptionAddressOrMask Thread-Index: AQHSglA1tWNI1KTDhki10VCwGCxTzKFh4tCg Date: Fri, 10 Feb 2017 08:00:37 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103B825D87@shsmsx102.ccr.corp.intel.com> References: <1486588386-2146-1-git-send-email-leo.duran@amd.com> <1486588386-2146-2-git-send-email-leo.duran@amd.com> In-Reply-To: <1486588386-2146-2-git-send-email-leo.duran@amd.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 1/3] MdeModulePkg: Add PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Feb 2017 08:00:41 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Star Zeng -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Leo = Duran Sent: Thursday, February 9, 2017 5:13 AM To: edk2-devel@ml01.01.org Cc: Laszlo Ersek ; Tian, Feng ; Bri= jesh Singh ; Zeng, Star ; Leo D= uran Subject: [edk2] [PATCH 1/3] MdeModulePkg: Add PCD PcdPteMemoryEncryptionAdd= ressOrMask From: Brijesh Singh This PCD holds the address mask for page table entries when memory encrypti= on is enabled on AMD processors supporting the Secure Encrypted Virtualizat= ion (SEV) feature. Cc: Feng Tian Cc: Star Zeng Cc: Laszlo Ersek Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 5 ++++- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 18 ++++++++++-------- MdeModulePkg/MdeModulePkg.dec | 8 ++++++++ 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index 2bc41be..d62bd9b 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -6,6 +6,8 @@ # needed to run the DXE Foundation. # # Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials # are licensed and made a= vailable under the terms and conditions of the BSD License # which accomp= anies this distribution. The full text of the license may be found at @@ -= 111,7 +113,8 @@ [FeaturePcd] gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress ## CONSUME= S =20 [Pcd.IA32,Pcd.X64] - gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## SOMETIM= ES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ##= SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask ##= CONSUMES =20 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64] gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIM= ES_CONSUMES diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 790f6ab..2c52389 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -16,6 +16,8 @@ 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:Sy= stem Programmer's Guide, Intel =20 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made availab= le under the terms and conditions of the BSD License which accompanies thi= s distribution. The full text of the license may be found at @@ -71,14 +73= ,14 @@ Split2MPageTo4K ( // // Fill in 2M page entry. // - *PageEntry2M =3D (UINT64) (UINTN) PageTableEntry | IA32_PG_P | IA32_PG_R= W; + *PageEntry2M =3D (UINT64) (UINTN) PageTableEntry | PcdGet64=20 + (PcdPteMemoryEncryptionAddressOrMask) | IA32_PG_P | IA32_PG_RW; =20 PhysicalAddress4K =3D PhysicalAddress; for (IndexOfPageTableEntries =3D 0; IndexOfPageTableEntries < 512; Index= OfPageTableEntries++, PageTableEntry++, PhysicalAddress4K +=3D SIZE_4KB) { // // Fill in the Page Table entries // - PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K; + PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K | PcdGet64=20 + (PcdPteMemoryEncryptionAddressOrMask); PageTableEntry->Bits.ReadWrite =3D 1; PageTableEntry->Bits.Present =3D 1; if ((PhysicalAddress4K >=3D StackBase) && (PhysicalAddress4K < StackBa= se + StackSize)) { @@ -116,7 +118,7 @@ Split1GPageTo2M ( // // Fill in 1G page entry. // - *PageEntry1G =3D (UINT64) (UINTN) PageDirectoryEntry | IA32_PG_P | IA32_= PG_RW; + *PageEntry1G =3D (UINT64) (UINTN) PageDirectoryEntry | PcdGet64=20 + (PcdPteMemoryEncryptionAddressOrMask) | IA32_PG_P | IA32_PG_RW; =20 PhysicalAddress2M =3D PhysicalAddress; for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries < 51= 2; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += =3D SIZE_2MB) { @@ -129,7 +131,7 @@ Split1GPageTo2M ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64) PhysicalAddress2M; + PageDirectoryEntry->Uint64 =3D (UINT64) PhysicalAddress2M |=20 + PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; @@ -248,7 +250,7 @@ CreateId= entityMappingPageTables ( // // Make a PML4 Entry // - PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEntr= y; + PageMapLevel4Entry->Uint64 =3D=20 + (UINT64)(UINTN)PageDirectoryPointerEntry | PcdGet64=20 + (PcdPteMemoryEncryptionAddressOrMask); PageMapLevel4Entry->Bits.ReadWrite =3D 1; PageMapLevel4Entry->Bits.Present =3D 1; =20 @@ -262,7 +264,7 @@ CreateIdentityMappingPageTables ( // // Fill in the Page Directory entries // - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress | PcdGet64= =20 + (PcdPteMemoryEncryptionAddressOrMask); PageDirectory1GEntry->Bits.ReadWrite =3D 1; PageDirectory1GEntry->Bits.Present =3D 1; PageDirectory1GEntry->Bits.MustBe1 =3D 1; @@ -280,7 +282,7 @@ Cr= eateIdentityMappingPageTables ( // // Fill in a Page Directory Pointer Entries // - PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirectory= Entry; + PageDirectoryPointerEntry->Uint64 =3D=20 + (UINT64)(UINTN)PageDirectoryEntry | PcdGet64=20 + (PcdPteMemoryEncryptionAddressOrMask); PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; PageDirectoryPointerEntry->Bits.Present =3D 1; =20 @@ -294,7 +296,7 @@ CreateIdentityMappingPageTables ( // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress; + PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress | PcdGet64= =20 + (PcdPteMemoryEncryptionAddressOrMask); PageDirectoryEntry->Bits.ReadWrite =3D 1; PageDirectoryEntry->Bits.Present =3D 1; PageDirectoryEntry->Bits.MustBe1 =3D 1; diff --git a/MdeModule= Pkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 273cd7e..15119d0= 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -6,6 +6,8 @@ # Copyright (c) 2007 - 2017, Intel Corporation. All rights reserved.
= # Copyright (c) 2016, Linaro Ltd. All rights reserved.
# (C) Copyright= 2016 Hewlett Packard Enterprise Development LP
+# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # This program and the accompanying materials are licensed and made availa= ble under # the terms and conditions of the BSD License that accompanies t= his distribution. # The full text of the license may be found at @@ -1682,6 +1684,12 @@ [Pcd= sFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] # @Prompt A list of system FMP ImageTypeId GUIDs gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x0}|= VOID*|0x30001046 =20 + ## This PCD holds the address mask for page table entries when memory=20 + encryption is # enabled on AMD processors supporting the Secure Encrypt= ed Virtualization (SEV) feature. + # This mask should be applied when creating 1:1 virtual to physical map= ping tables. + # + =20 + gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 + |UINT64|0x30001047 + [PcdsPatchableInModule] ## Specify memory size with page number for PEI code when # Loading Module at Fixed Address feature is enabled. -- 1.9.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel