From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CF38A81EE0 for ; Mon, 27 Feb 2017 16:59:16 -0800 (PST) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Feb 2017 16:59:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,216,1484035200"; d="scan'208";a="70887379" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga006.fm.intel.com with ESMTP; 27 Feb 2017 16:59:16 -0800 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 27 Feb 2017 16:59:16 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 27 Feb 2017 16:59:15 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.132]) with mapi id 14.03.0248.002; Tue, 28 Feb 2017 08:59:08 +0800 From: "Zeng, Star" To: "Duran, Leo" , "edk2-devel@ml01.01.org" CC: "Singh, Brijesh" , "Tian, Feng" , Laszlo Ersek , "Zeng, Star" Thread-Topic: [PATCH v4 1/6] MdeModulePkg: Add PCD PcdPteMemoryEncryptionAddressOrMask Thread-Index: AQHSkFfWOrfSNOoRr0az/d8u7iLpGKF8HSeAgABDP4CAATp/gA== Date: Tue, 28 Feb 2017 00:59:08 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103B82C87E@shsmsx102.ccr.corp.intel.com> References: <1488130987-2544-1-git-send-email-leo.duran@amd.com> <1488130987-2544-2-git-send-email-leo.duran@amd.com> <0C09AFA07DD0434D9E2A0C6AEB0483103B82C0D8@shsmsx102.ccr.corp.intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v4 1/6] MdeModulePkg: Add PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Feb 2017 00:59:17 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Star Zeng to MdeModulePkg changes. Thanks, Star -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Dura= n, Leo Sent: Monday, February 27, 2017 10:13 PM To: Zeng, Star ; edk2-devel@ml01.01.org Cc: Singh, Brijesh ; Tian, Feng ; Laszlo Ersek Subject: Re: [edk2] [PATCH v4 1/6] MdeModulePkg: Add PCD PcdPteMemoryEncryp= tionAddressOrMask Please see below. > -----Original Message----- > From: Zeng, Star [mailto:star.zeng@intel.com] > Sent: Sunday, February 26, 2017 8:20 PM > To: Duran, Leo ; edk2-devel@ml01.01.org > Cc: Tian, Feng ; Laszlo Ersek=20 > ; Singh, Brijesh ; Zeng,=20 > Star > Subject: RE: [PATCH v4 1/6] MdeModulePkg: Add PCD=20 > PcdPteMemoryEncryptionAddressOrMask >=20 > We saw you defined 4K/2M/1G in previous patch series, #define > PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull #define > PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull #define > PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull But only 1G mask is=20 > defined and used in this patch series, is that on purpose? > #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull >=20 > That means PcdPteMemoryEncryptionAddressOrMask will be just valid as=20 > 1G aligned, right? >=20 > Thanks, > Star [Duran, Leo] Correct... The mask *must* allow for 1G pages, so I've simplif= ied the logic. > -----Original Message----- > From: Leo Duran [mailto:leo.duran@amd.com] > Sent: Monday, February 27, 2017 1:43 AM > To: edk2-devel@ml01.01.org > Cc: Leo Duran ; Tian, Feng ;=20 > Zeng, Star ; Laszlo Ersek ;=20 > Brijesh Singh > Subject: [PATCH v4 1/6] MdeModulePkg: Add PCD=20 > PcdPteMemoryEncryptionAddressOrMask >=20 > This PCD holds the address mask for page table entries when memory=20 > encryption is enabled on AMD processors supporting the Secure=20 > Encrypted Virtualization (SEV) feature. >=20 > Cc: Feng Tian > Cc: Star Zeng > Cc: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Brijesh Singh > Signed-off-by: Leo Duran > Reviewed-by: Star Zeng > --- > MdeModulePkg/MdeModulePkg.dec | 8 ++++++++ > 1 file changed, 8 insertions(+) >=20 > diff --git a/MdeModulePkg/MdeModulePkg.dec=20 > b/MdeModulePkg/MdeModulePkg.dec index 426634f..f45ca84 100644 > --- a/MdeModulePkg/MdeModulePkg.dec > +++ b/MdeModulePkg/MdeModulePkg.dec > @@ -6,6 +6,8 @@ > # Copyright (c) 2007 - 2017, Intel Corporation. All rights=20 > reserved.
# Copyright (c) 2016, Linaro Ltd. All rights=20 > reserved.
# (C) Copyright 2016 Hewlett Packard Enterprise=20 > Development LP
> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# > # This program and the accompanying materials are licensed and made=20 > available under # the terms and conditions of the BSD License that=20 > accompanies this distribution. > # The full text of the license may be found at @@ -1702,6 +1704,12 @@ > # @Prompt A list of system FMP ImageTypeId GUIDs >=20 > gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGu > id|{0x0}|VOID*|0x30001046 >=20 > + ## This PCD holds the address mask for page table entries when=20 > + memory encryption is # enabled on AMD processors supporting the=20 > + Secure > Encrypted Virtualization (SEV) feature. > + # This mask should be applied when creating 1:1 virtual to=20 > + physical > mapping tables. > + # > + > + > gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrM > ask|0x0 > + |UINT64|0x30001047 > + > [PcdsPatchableInModule] > ## Specify memory size with page number for PEI code when > # Loading Module at Fixed Address feature is enabled. > -- > 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel