From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B3AE821A00AD9 for ; Wed, 28 Jun 2017 03:53:56 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Jun 2017 03:55:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,275,1496127600"; d="scan'208";a="1165590278" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by fmsmga001.fm.intel.com with ESMTP; 28 Jun 2017 03:55:27 -0700 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 28 Jun 2017 03:55:27 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 28 Jun 2017 03:55:26 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.146]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.197]) with mapi id 14.03.0319.002; Wed, 28 Jun 2017 18:55:25 +0800 From: "Zeng, Star" To: Ard Biesheuvel , "edk2-devel@lists.01.org" , "Dong, Eric" CC: "Tian, Feng" , "leif.lindholm@linaro.org" , "Zeng, Star" Thread-Topic: [PATCH v3] MdeModulePkg/AtaAtapiPassThru: relax PHY detect timeout Thread-Index: AQHS7/x+CEamGl11EEyDwezkDrxTLqI6GgLA Date: Wed, 28 Jun 2017 10:55:24 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103B8EF746@shsmsx102.ccr.corp.intel.com> References: <20170628105101.31525-1-ard.biesheuvel@linaro.org> In-Reply-To: <20170628105101.31525-1-ard.biesheuvel@linaro.org> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v3] MdeModulePkg/AtaAtapiPassThru: relax PHY detect timeout X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Jun 2017 10:53:56 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Star Zeng -----Original Message----- From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]=20 Sent: Wednesday, June 28, 2017 6:51 PM To: edk2-devel@lists.01.org; Zeng, Star ; Dong, Eric <= eric.dong@intel.com> Cc: Tian, Feng ; leif.lindholm@linaro.org; Ard Biesheu= vel Subject: [PATCH v3] MdeModulePkg/AtaAtapiPassThru: relax PHY detect timeout The SATA spec mandates that link detection by the PHY completes within 10 ms after receiving a reset signal. However, there is no obligation to up= hold this requirement at the driver end as strictly as we do, and as it tur= ns out, some combinations of host and device (e.g., Samsung 850 EVO connected to a LeMaker Cello) are only borderline compliant, which = means the device is not detected reliably. So let's allow for a bit of margin, and increase the PHY detect timeout val= ue to 15 ms. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- v3: update comment AhciModeInitialization() again MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 3 +-- MdeModulePkg/Bus= /Ata/AtaAtapiPassThru/AhciMode.h | 3 ++- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModulePk= g/Bus/Ata/AtaAtapiPassThru/AhciMode.c index 4d01c1dd7fca..b954de81015e 100644 --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c @@ -2376,8 +2376,7 @@ AhciModeInitialization ( AhciOrReg (PciIo, Offset, EFI_AHCI_PORT_CMD_FRE); =20 // - // Wait no longer than 10 ms to wait the Phy to detect the presence = of a device. - // It's the requirment from SATA1.0a spec section 5.2. + // Wait for the Phy to detect the presence of a device. // PhyDetectDelay =3D EFI_AHCI_BUS_PHY_DETECT_TIMEOUT; Offset =3D EFI_AHCI_PORT_START + Port * EFI_AHCI_PORT_REG_WIDTH + EF= I_AHCI_PORT_SSTS; diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMo= de.h b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h index 6401fb2e9fcd..809bcc307fc4 100644 --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.h @@ -41,8 +41,9 @@ typedef union { =20 // // Refer SATA1.0a spec section 5.2, the Phy detection time should be less = than 10ms. +// Add a bit of margin for robustness. // -#define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 10 +#define EFI_AHCI_BUS_PHY_DETECT_TIMEOUT 15 // // Refer SATA1.0a spec, the FIS enable time should be less than 500ms. // -- 2.9.3