From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 125BD21E11D2B for ; Sun, 27 Aug 2017 18:56:30 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP; 27 Aug 2017 18:59:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,439,1498546800"; d="scan'208";a="144491867" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga005.fm.intel.com with ESMTP; 27 Aug 2017 18:59:07 -0700 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 27 Aug 2017 18:59:07 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.319.2; Sun, 27 Aug 2017 18:59:06 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.39]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Mon, 28 Aug 2017 09:59:05 +0800 From: "Zeng, Star" To: Laszlo Ersek , "edk2-devel@lists.01.org" CC: "Yao, Jiewen" , "Dong, Eric" , "Zeng, Star" Thread-Topic: [edk2] [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Fix memory protection crash Thread-Index: AQHTHIf0iDrAg4RIVk2t8D1jiWakqKKUT9cAgACG1YD//5tSAIABeTNwgAIESoCAARmCkA== Date: Mon, 28 Aug 2017 01:59:04 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103B9294AB@shsmsx102.ccr.corp.intel.com> References: <1503544809-166388-1-git-send-email-star.zeng@intel.com> <0432078c-6490-139e-20d8-c6eac58ffd3f@redhat.com> <0C09AFA07DD0434D9E2A0C6AEB0483103B91DC10@shsmsx102.ccr.corp.intel.com> <50a6768d-77d9-c038-f5a1-62d9101bc6e4@redhat.com> <0C09AFA07DD0434D9E2A0C6AEB0483103B9232C1@shsmsx102.ccr.corp.intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Fix memory protection crash X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Aug 2017 01:56:30 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Thanks. :) Pushed this patch at https://github.com/tianocore/edk2/commit/714c2603018a9= 9a514c42c2b511c821f30ba9cdf. And sent the patch at https://lists.01.org/pipermail/edk2-devel/2017-August= /013768.html for the definition movement. Star -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Lasz= lo Ersek Sent: Monday, August 28, 2017 1:10 AM To: Zeng, Star ; edk2-devel@lists.01.org Cc: Yao, Jiewen ; Dong, Eric Subject: Re: [edk2] [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Fix memory protectio= n crash On 08/26/17 04:24, Zeng, Star wrote: > Laszlo, >=20 > I am ok to centralize the definition in the patch(V2 will cover it), how = about PiSmmCpuDxeSmm.c? Because I have now tested this patch (see below), at this point my preferen= ce would be that you commit v1 as-is, and then post a separate patch to cen= tralize the variable. (I wouldn't like to re-test because of the variable m= ovement.) I would have preferred to test v2 only, but the above works too I guess. > Have you helped get the test result with the patch? The crash is gone for the IA32 build, and I found no regressions in the IA32X64 build. Tested-by: Laszlo Ersek Thanks, Laszlo > -----Original Message----- > From: Laszlo Ersek [mailto:lersek@redhat.com] > Sent: Friday, August 25, 2017 7:52 PM > To: Zeng, Star ; edk2-devel@lists.01.org > Cc: Yao, Jiewen ; Dong, Eric=20 > > Subject: Re: [edk2] [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Fix memory=20 > protection crash >=20 > On 08/25/17 11:53, Zeng, Star wrote: >> Laszlo, >> >> X64 defined mPhysicalAddressBits already before the patch, and has the c= ode below to assign it. >> >> mPhysicalAddressBits =3D CalculateMaximumSupportAddress (); >=20 > Thanks. >=20 > Do you think it would make sense to centralize the definition (i.e.,=20 > the > allocation) of the mPhysicalAddressBits variable in this patch? >=20 > That is, > - instead of adding mPhysicalAddressBits to "Ia32/PageTbl.c", > - you could move it from "X64/PageTbl.c" to "SmmCpuMemoryManagement.c" > (or another C source file that is built into both Ia32 and X64). >=20 > Thanks, > Laszlo >=20 >> -----Original Message----- >> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf=20 >> Of Laszlo Ersek >> Sent: Friday, August 25, 2017 5:50 PM >> To: Zeng, Star ; edk2-devel@lists.01.org >> Cc: Yao, Jiewen ; Dong, Eric=20 >> >> Subject: Re: [edk2] [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Fix memory=20 >> protection crash >> >> Star, >> >> On 08/24/17 05:20, Star Zeng wrote: >>> https://bugzilla.tianocore.org/show_bug.cgi?id=3D624 reports memory=20 >>> protection crash in PiSmmCpuDxeSmm, Ia32 build with RAM above 4GB=20 >>> (of which 2GB are placed in 64-bit address). >>> It is because UEFI builds identity mapping page tables, >>>> 4G address is not supported at Ia32 build. >>> >>> This patch is to get the PhysicalAddressBits that is used to build=20 >>> in PageTbl.c(Ia32/X64), and use it to check whether the address is=20 >>> supported or not in ConvertMemoryPageAttributes(). >>> >>> With this patch, the debug messages will be like below. >>> UefiMemory protection: 0x0 - 0x9F000 Success UefiMemory protection:=20 >>> 0x100000 - 0x807000 Success UefiMemory protection: 0x808000 - >>> 0x810000 Success UefiMemory protection: 0x818000 - 0x820000 Success=20 >>> UefiMemory >>> protection: 0x1510000 - 0x7B798000 Success UefiMemory protection:=20 >>> 0x7B79B000 - 0x7E538000 Success UefiMemory protection: 0x7E539000 - >>> 0x7E545000 Success UefiMemory protection: 0x7E55A000 - 0x7E61F000=20 >>> Success UefiMemory protection: 0x7E62B000 - 0x7F6AB000 Success=20 >>> UefiMemory protection: 0x7F703000 - 0x7F70B000 Success UefiMemory >>> protection: 0x7F70F000 - 0x7F778000 Success UefiMemory protection:=20 >>> 0x100000000 - 0x180000000 Unsupported >>> >>> Cc: Jiewen Yao >>> Cc: Laszlo Ersek >>> Cc: Eric Dong >>> Originally-suggested-by: Jiewen Yao >>> Reported-by: Laszlo Ersek >>> Contributed-under: TianoCore Contribution Agreement 1.1 >>> Signed-off-by: Star Zeng >>> --- >>> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 4 +++ >>> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 1 + >>> UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 31 >>> +++++++++++++++++----- >>> 3 files changed, 30 insertions(+), 6 deletions(-) >>> >>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c >>> b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c >>> index 32ce5958c59c..e88b42d73343 100644 >>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c >>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c >>> @@ -16,6 +16,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EI= THER EXPRESS OR IMPLIED. >>> =20 >>> #include "PiSmmCpuDxeSmm.h" >>> =20 >>> +UINT8 mPhysicalAddressBits; >>> + >>> /** >>> Create PageTable for SMM use. >>> =20 >>> @@ -36,6 +38,8 @@ SmmInitPageTable ( >>> // >>> InitializeSpinLock (mPFLock); >>> =20 >>> + mPhysicalAddressBits =3D 32; >>> + >>> if (FeaturePcdGet (PcdCpuSmmProfileEnable)) { >>> // >>> // Set own Page Fault entry instead of the default one, because=20 >>> SMM Profile diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h >>> b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h >>> index dbce9ec520fe..1cf85c1481a7 100644 >>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h >>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h >>> @@ -419,6 +419,7 @@ extern SPIN_LOCK *mConfig= SmmCodeAccessCheckLock; >>> extern SPIN_LOCK *mMemoryMappedLock; >>> extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges; >>> extern UINTN mSmmCpuSmramRangeCount; >>> +extern UINT8 mPhysicalAddressBits; >>> =20 >>> // >>> // Copy of the PcdPteMemoryEncryptionAddressOrMask >>> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c >>> b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c >>> index a535389c26ce..3ad5256f1e03 100644 >>> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c >>> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c >>> @@ -1,6 +1,6 @@ >>> /** @file >>> =20 >>> -Copyright (c) 2016, Intel Corporation. All rights reserved.
>>> +Copyright (c) 2016 - 2017, Intel Corporation. All rights=20 >>> +reserved.
>>> This program and the accompanying materials are licensed and made=20 >>> available under the terms and conditions of the BSD License which=20 >>> accompanies this distribution. The full text of the license may be=20 >>> found at @@ -380,6 +380,7 @@ ConvertMemoryPageAttributes ( >>> PAGE_ATTRIBUTE SplitAttribute; >>> RETURN_STATUS Status; >>> BOOLEAN IsEntryModified; >>> + EFI_PHYSICAL_ADDRESS MaximumSupportMemAddress; >>> =20 >>> ASSERT (Attributes !=3D 0); >>> ASSERT ((Attributes & ~(EFI_MEMORY_RP | EFI_MEMORY_RO | >>> EFI_MEMORY_XP)) =3D=3D 0); @@ -391,6 +392,17 @@ ConvertMemoryPageAttrib= utes ( >>> return RETURN_INVALID_PARAMETER; >>> } >>> =20 >>> + MaximumSupportMemAddress =3D=20 >>> + (EFI_PHYSICAL_ADDRESS)(UINTN)(LShiftU64 >>> + (1, mPhysicalAddressBits) - 1); if (BaseAddress > MaximumSupportMemA= ddress) { >>> + return RETURN_UNSUPPORTED; >>> + } >>> + if (Length > MaximumSupportMemAddress) { >>> + return RETURN_UNSUPPORTED; >>> + } >>> + if ((Length !=3D 0) && (BaseAddress > MaximumSupportMemAddress - (Le= ngth - 1))) { >>> + return RETURN_UNSUPPORTED; >>> + } >>> + >>> // DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx,=20 >>> %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes)); >>> =20 >>> if (IsSplitted !=3D NULL) { >>> @@ -1037,6 +1049,7 @@ SetUefiMemMapAttributes ( >>> VOID >>> ) >>> { >>> + EFI_STATUS Status; >>> EFI_MEMORY_DESCRIPTOR *MemoryMap; >>> UINTN MemoryMapEntryCount; >>> UINTN Index; >>> @@ -1052,12 +1065,18 @@ SetUefiMemMapAttributes ( >>> MemoryMap =3D mUefiMemoryMap; >>> for (Index =3D 0; Index < MemoryMapEntryCount; Index++) { >>> if (IsUefiPageNotPresent(MemoryMap)) { >>> - DEBUG ((DEBUG_INFO, "UefiMemory protection: 0x%lx - 0x%lx\n", Me= moryMap->PhysicalStart, MemoryMap->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZ= E((UINTN)MemoryMap->NumberOfPages))); >>> - SmmSetMemoryAttributes ( >>> + Status =3D SmmSetMemoryAttributes ( >>> + MemoryMap->PhysicalStart, >>> + EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages), >>> + EFI_MEMORY_RP >>> + ); >>> + DEBUG (( >>> + DEBUG_INFO, >>> + "UefiMemory protection: 0x%lx - 0x%lx %r\n", >>> MemoryMap->PhysicalStart, >>> - EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages), >>> - EFI_MEMORY_RP >>> - ); >>> + MemoryMap->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE((UINTN)Me= moryMap->NumberOfPages), >>> + Status >>> + )); >>> } >>> MemoryMap =3D NEXT_MEMORY_DESCRIPTOR(MemoryMap, mUefiDescriptorSiz= e); >>> } >>> >> >> before applying this patch for local testing, I figured I'd look it over= quickly. >> >> I think that you missed adding the X64 changes to the commit, with=20 >> "git add". Because, the "mPhysicalAddressBits" variable is declared=20 >> in common code, it is also consumed in common code, but it is only=20 >> defined (i.e., >> allocated) and set in Ia32 code. I believe that applying this exact patc= h would prevent PiSmmCpuDxeSmm even from linking. >> >> I think for X64 you likely have a change similar to the Ia32 one (defini= ng the variable and setting it to the actual physical address bits, likely = from the CPU HOB), but it's not part of the patch. >> >> If I'm right and you decide to post v2, then I suggest another (very >> small) improvement: I think the definition (=3Dallocation) of "mPhysical= AddressBits" could also be moved to common code; only the assignments have = to be architecture-specific. >> >> Thanks >> Laszlo >> _______________________________________________ >> edk2-devel mailing list >> edk2-devel@lists.01.org >> https://lists.01.org/mailman/listinfo/edk2-devel >> _______________________________________________ >> edk2-devel mailing list >> edk2-devel@lists.01.org >> https://lists.01.org/mailman/listinfo/edk2-devel >> >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel >=20 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel