From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C0F8821E8796F for ; Wed, 13 Sep 2017 03:10:40 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP; 13 Sep 2017 03:13:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,387,1500966000"; d="scan'208";a="128303163" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga004.jf.intel.com with ESMTP; 13 Sep 2017 03:13:38 -0700 Received: from fmsmsx118.amr.corp.intel.com (10.18.116.18) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 13 Sep 2017 03:13:37 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx118.amr.corp.intel.com (10.18.116.18) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 13 Sep 2017 03:13:37 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.39]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Wed, 13 Sep 2017 18:13:35 +0800 From: "Zeng, Star" To: "Yao, Jiewen" , "edk2-devel@lists.01.org" CC: "Zeng, Star" Thread-Topic: [edk2] [PATCH 00/11] Add IOMMU PEI support. Thread-Index: AQHTKLR2uTOt5R1XEUWHxTlYuefifKKynk0w Date: Wed, 13 Sep 2017 10:13:34 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103B940CE2@shsmsx102.ccr.corp.intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> In-Reply-To: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 00/11] Add IOMMU PEI support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Sep 2017 10:10:41 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I have been confused by where should new module be put for some time. When should a new module be put at XXXPkg/Universal? For example, MdeModule= /Universal, UefiCpuPkg/Universal, .... When should a new module be put at XXXPkg/Feature? For example, UefiCpuPkg/= Feature. When should a new module be put at the root of a package folder? For exampl= e, UefiCpuPkg/PiSmmCpuDxeSmm, IntelSiliconPkg/IntelVTdDxe, .... Is it better or not to put IntelVTdDxe, PlatformVTdSampleDxe and new IntelV= TdPmrPei, PlatformVTdInfoSamplePei in IntelSiliconPkg/Feature/VTd together? Thanks, Star -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Jiew= en Yao Sent: Friday, September 8, 2017 11:04 PM To: edk2-devel@lists.01.org Subject: [edk2] [PATCH 00/11] Add IOMMU PEI support. This series patch added IOMMU PEI support. It is also posted to https://github.com/jyao1/edk2/tree/IoMmuPpi. 1) Patch 1 and 2 add EDKII_IOMMU_PPI. It is similar to EDKII_IOMMU_PROTOCOL. 2) Patch 3 and 4 add Intel VTD PMR register support for DXE phase IntelVTdD= xe. This is to prepare handle PMR usage in PEI phase. 3) Patch 5 and 6 add EDKII_VTD_INFO_PPI. This PPI is to provide Intel VTD information in PEI. In DXE, the VTd driver can get VTD info from ACPI DMAR table. But in PEI, there is no way to get VTD info before. VTD_INFO_PPI is added to resolve the problem. 4) Patch 7 and 8 add IntelVTdPmrPei driver. This driver consumes EDKII_VTD_INFO_PPI and produces IOMMU_PPI. It enables VTD PMR register to provide DMA protection. The PMR based DMA protection is a simple solution to mark 2 regions can be = DMA protected. The IntelVTdPmrPei allocates a small chunk buffer for DMA and protect the r= est memory. 5) Patch 9 and 10 add a sample VTdInfo PEI driver. It provides a sample to show how to report VTd info in PEI phase. 6) Patch 11 updates XhciPei driver to consume IOMMU_PPI. If the IOMMU_PPI is present, XhciPei will use IOMMU_PPI to allocate DMA buf= fer. Or the XhciPei will still use old way - PeiServiceAllocatePage to allo= cate DRAM as DMA buffer. This is the first PEI device driver consuming IOMMU_PPI to show the concept= . The rest PEI device drivers will be updated in separated patches. This series patch is validated on Intel Kabylake Platform. 1) We can use XHCI to do file transfer in PEI phase, 2) We can still use XHCI in DXE phase, such as shell environment. 3) If the device driver does not consume IOMMU_PPI, the DMA fails. Jiewen Yao (11): MdeModulePkg/Include: Add IOMMU_PPI. MdeModulePkg/Dec: Add IOMMU_PPI GUID. IntelSiliconPkg/Vtd.h: Add definition for PMR. IntelSiliconPkg/VTdDxe: Disable PMR IntelSiliconPkg/include: Add VTD_INFO PPI. IntelSiliconPkg/dec: Add VTD_INFO PPI GUID IntelSiliconPkg: Add IntelVTdPmrPei. IntelSiliconPkg/dsc: Add IntelVTdPmrPeim. IntelSiliconPkg: Add PlatformVTdInfoSamplePei. IntelSiliconPkg/dsc: Add PlatformVTdInfoSamplePei. MdeModulePkg/XhciPei: Support IoMmu. IntelSiliconPkg/Include/IndustryStandard/Vtd.h = | 6 + IntelSiliconPkg/Include/Ppi/VtdInfo.h = | 40 ++ IntelSiliconPkg/IntelSiliconPkg.dec = | 3 + IntelSiliconPkg/IntelSiliconPkg.dsc = | 10 + IntelSiliconPkg/IntelVTdDxe/VtdReg.c = | 51 +- IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c = | 314 ++++++++++ IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.c = | 615 ++++++++++++++++++++ IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.h = | 68 +++ IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf = | 59 ++ IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.uni = | 20 + IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni = | 20 + IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c = | 65 +++ IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf = | 51 ++ IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.uni = | 20 + IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePeiExtra.uni= | 20 + MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c = | 249 ++++++++ MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c = | 55 +- MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h = | 9 +- MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.c = | 55 +- MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h = | 107 ++++ MdeModulePkg/Bus/Pci/XhciPei/XhciPei.inf = | 3 + MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c = | 47 +- MdeModulePkg/Bus/Pci/XhciPei/XhciSched.h = | 1 + MdeModulePkg/Include/Ppi/IoMmu.h = | 196 +++++++ MdeModulePkg/MdeModulePkg.dec = | 3 + 25 files changed, 2052 insertions(+), 35 deletions(-) create mode 100644 = IntelSiliconPkg/Include/Ppi/VtdInfo.h create mode 100644 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmr.c create mode 100644 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.c create mode 100644 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.h create mode 100644 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.inf create mode 100644 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPei.uni create mode 100644 IntelSiliconPkg/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni create mode 100644 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInf= oSamplePei.c create mode 100644 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInf= oSamplePei.inf create mode 100644 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInf= oSamplePei.uni create mode 100644 IntelSiliconPkg/PlatformVTdInfoSamplePei/PlatformVTdInf= oSamplePeiExtra.uni create mode 100644 MdeModulePkg/Bus/Pci/XhciPei/DmaMem.c create mode 100644 MdeModulePkg/Include/Ppi/IoMmu.h -- 2.7.4.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel