From: "Zeng, Star" <star.zeng@intel.com>
To: "Yao, Jiewen" <jiewen.yao@intel.com>,
"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: "Zeng, Star" <star.zeng@intel.com>
Subject: Re: [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR
Date: Thu, 14 Sep 2017 05:35:46 +0000 [thread overview]
Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103B952715@SHSMSX151.ccr.corp.intel.com> (raw)
In-Reply-To: <1504883034-22060-5-git-send-email-jiewen.yao@intel.com>
A minor comment.
Should or need IntelVTdPmrPei disable PMR at endofpei?
Thanks,
Star
-----Original Message-----
From: Yao, Jiewen
Sent: Friday, September 8, 2017 11:04 PM
To: edk2-devel@lists.01.org
Cc: Zeng, Star <star.zeng@intel.com>
Subject: [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR
When VTd translation is enabled, PMR can be disable.
Or the DMA will be blocked by PMR.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
---
IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 51 +++++++++++++++++++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
index 7402d81..1404af7 100644
--- a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
+++ b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c
@@ -196,6 +196,39 @@ PrepareVtdConfig (
}
/**
+ Disable PMR in all VTd engine.
+**/
+VOID
+DisablePmr (
+ VOID
+ )
+{
+ UINT32 Reg32;
+ VTD_CAP_REG CapReg;
+ UINTN Index;
+
+ DEBUG ((DEBUG_INFO,"DisablePmr\n"));
+ for (Index = 0; Index < mVtdUnitNumber; Index++) {
+ CapReg.Uint64 = MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_CAP_REG);
+ if (CapReg.Bits.PLMR == 0 || CapReg.Bits.PHMR == 0) {
+ continue ;
+ }
+
+ Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG);
+ if ((Reg32 & BIT0) != 0) {
+ MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG, 0x0);
+ do {
+ Reg32 = MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_ENABLE_REG);
+ } while((Reg32 & BIT0) != 0);
+ DEBUG ((DEBUG_INFO,"Pmr(%d) disabled\n", Index));
+ } else {
+ DEBUG ((DEBUG_INFO,"Pmr(%d) not enabled\n", Index));
+ }
+ }
+ return ;
+}
+
+/**
Enable DMAR translation.
@retval EFI_SUCCESS DMAR translation is enabled.
@@ -259,6 +292,11 @@ EnableDmar (
DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index));
}
+ //
+ // Need disable PMR, since we already setup translation table.
+ //
+ DisablePmr ();
+
mVtdEnabled = TRUE;
return EFI_SUCCESS;
@@ -502,7 +540,7 @@ DumpVtdIfError (
for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
FrcdReg.Uint64[0] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG));
FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
- if ((FrcdReg.Uint64[0] != 0) || (FrcdReg.Uint64[1] != 0)) {
+ if (FrcdReg.Bits.F != 0) {
HasError = TRUE;
}
}
@@ -511,6 +549,17 @@ DumpVtdIfError (
DEBUG((DEBUG_INFO, "\n#### ERROR ####\n"));
DumpVtdRegs (Num);
DEBUG((DEBUG_INFO, "#### ERROR ####\n\n"));
+ //
+ // Clear
+ //
+ for (Index = 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) {
+ FrcdReg.Uint64[1] = MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)));
+ if (FrcdReg.Bits.F != 0) {
+ FrcdReg.Bits.F = 0;
+ MmioWrite64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)), FrcdReg.Uint64[1]);
+ }
+ MmioWrite32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG, MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG));
+ }
}
}
}
--
2.7.4.windows.1
next prev parent reply other threads:[~2017-09-14 5:32 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-08 15:03 [PATCH 00/11] Add IOMMU PEI support Jiewen Yao
2017-09-08 15:03 ` [PATCH 01/11] MdeModulePkg/Include: Add IOMMU_PPI Jiewen Yao
2017-09-08 15:03 ` [PATCH 02/11] MdeModulePkg/Dec: Add IOMMU_PPI GUID Jiewen Yao
2017-09-08 15:03 ` [PATCH 03/11] IntelSiliconPkg/Vtd.h: Add definition for PMR Jiewen Yao
2017-09-08 15:03 ` [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR Jiewen Yao
2017-09-14 5:35 ` Zeng, Star [this message]
2017-09-14 6:02 ` Yao, Jiewen
2017-09-14 6:10 ` Zeng, Star
2017-09-14 6:15 ` Yao, Jiewen
2017-09-08 15:03 ` [PATCH 05/11] IntelSiliconPkg/include: Add VTD_INFO PPI Jiewen Yao
2017-09-08 15:03 ` [PATCH 06/11] IntelSiliconPkg/dec: Add VTD_INFO PPI GUID Jiewen Yao
2017-09-08 15:03 ` [PATCH 07/11] IntelSiliconPkg: Add IntelVTdPmrPei Jiewen Yao
2017-09-08 15:03 ` [PATCH 08/11] IntelSiliconPkg/dsc: Add IntelVTdPmrPeim Jiewen Yao
2017-09-08 15:03 ` [PATCH 09/11] IntelSiliconPkg: Add PlatformVTdInfoSamplePei Jiewen Yao
2017-09-08 15:03 ` [PATCH 10/11] IntelSiliconPkg/dsc: " Jiewen Yao
2017-09-08 15:03 ` [PATCH 11/11] MdeModulePkg/XhciPei: Support IoMmu Jiewen Yao
2017-09-13 10:13 ` [PATCH 00/11] Add IOMMU PEI support Zeng, Star
2017-09-13 10:19 ` Yao, Jiewen
2017-09-14 6:32 ` Zeng, Star
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