From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 85E4E21E87993 for ; Wed, 13 Sep 2017 22:32:51 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Sep 2017 22:35:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,391,1500966000"; d="scan'208";a="151144139" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga005.fm.intel.com with ESMTP; 13 Sep 2017 22:35:49 -0700 Received: from fmsmsx117.amr.corp.intel.com (10.18.116.17) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 13 Sep 2017 22:35:49 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx117.amr.corp.intel.com (10.18.116.17) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 13 Sep 2017 22:35:48 -0700 Received: from shsmsx151.ccr.corp.intel.com ([169.254.3.98]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.168]) with mapi id 14.03.0319.002; Thu, 14 Sep 2017 13:35:47 +0800 From: "Zeng, Star" To: "Yao, Jiewen" , "edk2-devel@lists.01.org" CC: "Zeng, Star" Thread-Topic: [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR Thread-Index: AQHTKLPCe8Cw2FMzPkmKHFIp22ODcaKz5OFw Date: Thu, 14 Sep 2017 05:35:46 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103B952715@SHSMSX151.ccr.corp.intel.com> References: <1504883034-22060-1-git-send-email-jiewen.yao@intel.com> <1504883034-22060-5-git-send-email-jiewen.yao@intel.com> In-Reply-To: <1504883034-22060-5-git-send-email-jiewen.yao@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Sep 2017 05:32:51 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable A minor comment. Should or need IntelVTdPmrPei disable PMR at endofpei? Thanks, Star -----Original Message----- From: Yao, Jiewen=20 Sent: Friday, September 8, 2017 11:04 PM To: edk2-devel@lists.01.org Cc: Zeng, Star Subject: [PATCH 04/11] IntelSiliconPkg/VTdDxe: Disable PMR When VTd translation is enabled, PMR can be disable. Or the DMA will be blocked by PMR. Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jiewen Yao --- IntelSiliconPkg/IntelVTdDxe/VtdReg.c | 51 +++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c b/IntelSiliconPkg/IntelVT= dDxe/VtdReg.c index 7402d81..1404af7 100644 --- a/IntelSiliconPkg/IntelVTdDxe/VtdReg.c +++ b/IntelSiliconPkg/IntelVTdDxe/VtdReg.c @@ -196,6 +196,39 @@ PrepareVtdConfig ( } =20 /** + Disable PMR in all VTd engine. +**/ +VOID +DisablePmr ( + VOID + ) +{ + UINT32 Reg32; + VTD_CAP_REG CapReg; + UINTN Index; + + DEBUG ((DEBUG_INFO,"DisablePmr\n")); + for (Index =3D 0; Index < mVtdUnitNumber; Index++) { + CapReg.Uint64 =3D MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAd= dress + R_CAP_REG); + if (CapReg.Bits.PLMR =3D=3D 0 || CapReg.Bits.PHMR =3D=3D 0) { + continue ; + } + + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_PMEN_ENABLE_REG); + if ((Reg32 & BIT0) !=3D 0) { + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_= ENABLE_REG, 0x0); + do { + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddres= s + R_PMEN_ENABLE_REG); + } while((Reg32 & BIT0) !=3D 0); + DEBUG ((DEBUG_INFO,"Pmr(%d) disabled\n", Index)); + } else { + DEBUG ((DEBUG_INFO,"Pmr(%d) not enabled\n", Index)); + } + } + return ; +} + +/** Enable DMAR translation. =20 @retval EFI_SUCCESS DMAR translation is enabled. @@ -259,6 +292,11 @@ EnableDmar ( DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index)); } =20 + // + // Need disable PMR, since we already setup translation table. + // + DisablePmr (); + mVtdEnabled =3D TRUE; =20 return EFI_SUCCESS; @@ -502,7 +540,7 @@ DumpVtdIfError ( for (Index =3D 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) { FrcdReg.Uint64[0] =3D MmioRead64 (mVtdUnitInformation[Num].VtdUnitBa= seAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG)); FrcdReg.Uint64[1] =3D MmioRead64 (mVtdUnitInformation[Num].VtdUnitBa= seAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UI= NT64))); - if ((FrcdReg.Uint64[0] !=3D 0) || (FrcdReg.Uint64[1] !=3D 0)) { + if (FrcdReg.Bits.F !=3D 0) { HasError =3D TRUE; } } @@ -511,6 +549,17 @@ DumpVtdIfError ( DEBUG((DEBUG_INFO, "\n#### ERROR ####\n")); DumpVtdRegs (Num); DEBUG((DEBUG_INFO, "#### ERROR ####\n\n")); + // + // Clear + // + for (Index =3D 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) { + FrcdReg.Uint64[1] =3D MmioRead64 (mVtdUnitInformation[Num].VtdUnit= BaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(= UINT64))); + if (FrcdReg.Bits.F !=3D 0) { + FrcdReg.Bits.F =3D 0; + MmioWrite64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((Cap= Reg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)), FrcdReg.U= int64[1]); + } + MmioWrite32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_= REG, MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG))= ; + } } } } --=20 2.7.4.windows.1