From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.88; helo=mga01.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 05D5821F2AF74 for ; Thu, 28 Sep 2017 02:27:32 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Sep 2017 02:30:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,449,1500966000"; d="scan'208";a="156490079" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga005.fm.intel.com with ESMTP; 28 Sep 2017 02:30:47 -0700 Received: from fmsmsx153.amr.corp.intel.com (10.18.125.6) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 28 Sep 2017 02:30:46 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX153.amr.corp.intel.com (10.18.125.6) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 28 Sep 2017 02:30:45 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.175]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Thu, 28 Sep 2017 17:30:44 +0800 From: "Zeng, Star" To: "Dong, Eric" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" , "Yao, Jiewen" , "Zeng, Star" Thread-Topic: [edk2] [Patch 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Refine code to avoid duplicated code. Thread-Index: AQHTODpgJS7JDCCrD0+wTFWqL9Ek0aLKBuiA Date: Thu, 28 Sep 2017 09:30:44 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103B97C4C7@shsmsx102.ccr.corp.intel.com> References: <1506590107-7324-1-git-send-email-eric.dong@intel.com> <1506590107-7324-3-git-send-email-eric.dong@intel.com> In-Reply-To: <1506590107-7324-3-git-send-email-eric.dong@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Refine code to avoid duplicated code. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Sep 2017 09:27:33 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Just FYI, another idea is to declare SetProcessorRegister() like below, the= n the caller of SetProcessorRegister() has no need to touch mAcpiCpuData. VOID SetProcessorRegister ( IN BOOLEAN PreSmmFlag ) { CPU_REGISTER_TABLE *RegisterTableList; ... if (PreSmmFlag) { RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSm= mInitRegisterTable; } else { RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.Regis= terTable; } ... Thanks, Star -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Eric= Dong Sent: Thursday, September 28, 2017 5:15 PM To: edk2-devel@lists.01.org Cc: Ni, Ruiyu ; Yao, Jiewen Subject: [edk2] [Patch 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Refine code to avoid= duplicated code. Refine code to avoid duplicate code to set processor register. Cc: Jiewen Yao Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 78 ++++++++++-------------------------= ---- 1 file changed, 20 insertions(+), 58 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index ae4b516..500a0e2 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -208,18 +208,28 @@ Returns: =20 This function programs registers for the calling processor. =20 - @param RegisterTable Pointer to register table of the running processor= . + @param RegisterTableList Pointer to register table of the running p= rocessor. =20 **/ VOID SetProcessorRegister ( - IN CPU_REGISTER_TABLE *RegisterTable + IN CPU_REGISTER_TABLE *RegisterTableList ) { CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; UINTN Index; UINTN Value; SPIN_LOCK *MsrSpinLock; + UINT32 InitApicId; + CPU_REGISTER_TABLE *RegisterTable; + + InitApicId =3D GetInitialApicId (); + for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { + if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { + RegisterTable =3D &RegisterTableList[Index]; + break; + } + } =20 // // Traverse Register Table of this logical processor @@ -347,8 +357,6 @@= SetProcessorRegister ( } } =20 - - /** AP initialization before then after SMBASE relocation in the S3 boot pat= h. **/ @@ -357,26 +365,12 @@ MPRendezvousProcedure ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; UINTN TopOfStack; UINT8 Stack[128]; =20 LoadMtrrData (mAcpiCpuData.MtrrTable); =20 - // - // Find processor number for this CPU. - // - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmm= InitRegisterTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } - + SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN)=20 + mAcpiCpuData.PreSmmInitRegisterTable); =20 // // Count down the number with lock mechanism. @@ -393,14 +387,7 @@ MPRendezvousProcedure ( ProgramVirtualWireMode (); DisableLvtInterrupts (); =20 - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.Regist= erTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN)=20 + mAcpiCpuData.RegisterTable); =20 // // Place AP into the safe code, count down the number with lock mechanis= m in the safe code. @@ -475,27 +462,13 @@ PrepareApStartupVector ( =20 **/ VOID -EarlyInitializeCpu ( +InitializeCpuBeforeRebase ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; - LoadMtrrData (mAcpiCpuData.MtrrTable); =20 - // - // Find processor number for this CPU. - // - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.PreSmm= InitRegisterTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN)=20 + mAcpiCpuData.PreSmmInitRegisterTable); =20 ProgramVirtualWireMode (); =20 @@ -527,22 +500,11 @@ EarlyInitializeCpu ( =20 **/ VOID -InitializeCpu ( +InitializeCpuAfterRebase ( VOID ) { - CPU_REGISTER_TABLE *RegisterTableList; - UINT32 InitApicId; - UINTN Index; - - RegisterTableList =3D (CPU_REGISTER_TABLE *) (UINTN) mAcpiCpuData.Regist= erTable; - InitApicId =3D GetInitialApicId (); - for (Index =3D 0; Index < mAcpiCpuData.NumberOfCpus; Index++) { - if (RegisterTableList[Index].InitialApicId =3D=3D InitApicId) { - SetProcessorRegister (&RegisterTableList[Index]); - break; - } - } + SetProcessorRegister ((CPU_REGISTER_TABLE *) (UINTN)=20 + mAcpiCpuData.RegisterTable); =20 mNumberToFinish =3D mAcpiCpuData.NumberOfCpus - 1; =20 @@ -660,7 +622,7 @@ SmmRestoreCpu ( // // First time microcode load and restore MTRRs // - EarlyInitializeCpu (); + InitializeCpuBeforeRebase (); } =20 // @@ -675,7 +637,7 @@ SmmRestoreCpu ( // // Restore MSRs for BSP and all APs // - InitializeCpu (); + InitializeCpuAfterRebase (); } =20 // -- 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel