From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Permerror (SPF Permanent Error: More than 10 MX records returned) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CFB402216D8C4 for ; Thu, 14 Dec 2017 19:13:54 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Dec 2017 19:18:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,402,1508828400"; d="scan'208";a="18399704" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga002.jf.intel.com with ESMTP; 14 Dec 2017 19:18:35 -0800 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 14 Dec 2017 19:18:35 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 14 Dec 2017 19:18:35 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.175]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.213]) with mapi id 14.03.0319.002; Fri, 15 Dec 2017 11:18:33 +0800 From: "Zeng, Star" To: "Wang, Jian J" , "edk2-devel@lists.01.org" CC: "Ni, Ruiyu" , "Dong, Eric" , "Zeng, Star" Thread-Topic: [PATCH] MdeModulePkg/DxeIplPeim: fix incorrect page table split during protecting Thread-Index: AQHTdU3dtOOV2hbxCkeKVD3bkhKX9qNDvBSA Date: Fri, 15 Dec 2017 03:18:32 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103B9C3F1B@shsmsx102.ccr.corp.intel.com> References: <20171215023838.9400-1-jian.j.wang@intel.com> In-Reply-To: <20171215023838.9400-1-jian.j.wang@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdeModulePkg/DxeIplPeim: fix incorrect page table split during protecting X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Dec 2017 03:13:55 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Star Zeng -----Original Message----- From: Wang, Jian J=20 Sent: Friday, December 15, 2017 10:39 AM To: edk2-devel@lists.01.org Cc: Ni, Ruiyu ; Zeng, Star ; Dong,= Eric Subject: [PATCH] MdeModulePkg/DxeIplPeim: fix incorrect page table split du= ring protecting The root cause of this issue is that, during splitting page table, the page= size should be the value of next level (smaller one) instead of current le= vel. The wrong page size will then cause wrong page table introduced, which will= break the normal boot. Validation works include booting to Windows 10 and Fedora 26 on real Intel = platform and OVMF emulated platform in addition to manual checks on page ta= ble with JTAG tool. Cc: Ruiyu Ni Cc: Star Zeng Cc: Eric Dong Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang --- MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 26116e420c..bbdfa2bb8e 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -472,6 +472,8 @@ SetPageTablePoolReadOnly ( // // The smaller granularity of page must be needed. // + ASSERT (Level > 1); + NewPageTable =3D AllocatePageTableMemory (1); ASSERT (NewPageTable !=3D NULL); =20 @@ -481,10 +483,10 @@ SetPageTablePoolReadOnly ( ++EntryIndex) { NewPageTable[EntryIndex] =3D PhysicalAddress | AddressEncMask | IA32_PG_P | IA32_PG_RW; - if (Level > 1) { + if (Level > 2) { NewPageTable[EntryIndex] |=3D IA32_PG_PS; } - PhysicalAddress +=3D LevelSize[Level]; + PhysicalAddress +=3D LevelSize[Level - 1]; } =20 PageTable[Index] =3D (UINT64)(UINTN)NewPageTable | AddressEncMask | -- 2.14.1.windows.1