From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F2B1D222A54FF for ; Wed, 3 Jan 2018 22:12:57 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Jan 2018 22:18:00 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,506,1508828400"; d="scan'208";a="7121953" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga007.fm.intel.com with ESMTP; 03 Jan 2018 22:18:00 -0800 Received: from fmsmsx126.amr.corp.intel.com (10.18.125.43) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 3 Jan 2018 22:18:00 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX126.amr.corp.intel.com (10.18.125.43) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 3 Jan 2018 22:17:59 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.189]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Thu, 4 Jan 2018 14:17:57 +0800 From: "Zeng, Star" To: "Yao, Jiewen" , "edk2-devel@lists.01.org" CC: "Zeng, Star" Thread-Topic: [PATCH] IntelSiliconPkg IntelVTdDxe: Use TPL to protect list/engine operation Thread-Index: AQHThQyotLnD8xQW/ke/cqyyjG4hiKNitiwAgAAA+wCAAIYt4A== Date: Thu, 4 Jan 2018 06:17:56 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103B9F5119@shsmsx102.ccr.corp.intel.com> References: <1515036740-16812-1-git-send-email-star.zeng@intel.com> <74D8A39837DF1E4DA445A8C0B3885C503AA6FDBB@shsmsx102.ccr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C503AA6FDEF@shsmsx102.ccr.corp.intel.com> In-Reply-To: <74D8A39837DF1E4DA445A8C0B3885C503AA6FDEF@shsmsx102.ccr.corp.intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] IntelSiliconPkg IntelVTdDxe: Use TPL to protect list/engine operation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Jan 2018 06:12:58 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Got it and agree. I will keep TPL_CALLBACK for ExitBootServices/LegacyBoot. Thanks, Star -----Original Message----- From: Yao, Jiewen=20 Sent: Thursday, January 4, 2018 2:17 PM To: Yao, Jiewen ; Zeng, Star ; e= dk2-devel@lists.01.org Subject: RE: [PATCH] IntelSiliconPkg IntelVTdDxe: Use TPL to protect list/e= ngine operation Correct typo. > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of=20 > Yao, Jiewen > Sent: Thursday, January 4, 2018 2:14 PM > To: Zeng, Star ; edk2-devel@lists.01.org > Subject: Re: [edk2] [PATCH] IntelSiliconPkg IntelVTdDxe: Use TPL to=20 > protect list/engine operation >=20 > It is good to have lock for linked list management. >=20 > However, I do not think we should update TPL for ExitBootServices/LegacyB= oot. >=20 > I purposely use TPL_CALLBACK to make sure VTd is tear down later, so=20 > that other driver can stop DMA before that. >=20 > Thank you > Yao Jiewen >=20 > > -----Original Message----- > > From: Zeng, Star > > Sent: Thursday, January 4, 2018 11:32 AM > > To: edk2-devel@lists.01.org > > Cc: Zeng, Star ; Yao, Jiewen=20 > > > > Subject: [PATCH] IntelSiliconPkg IntelVTdDxe: Use TPL to protect=20 > > list/engine operation > > > > Cc: Jiewen Yao > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Star Zeng > > --- > > IntelSiliconPkg/Feature/VTd/IntelVTdDxe/BmDma.c | 19 ++++++------- > > .../Feature/VTd/IntelVTdDxe/DmaProtection.c | 8 +++--- > > .../Feature/VTd/IntelVTdDxe/DmaProtection.h | 2 ++ > > .../Feature/VTd/IntelVTdDxe/IntelVTdDxe.c | 32 > > +++++++++------------- > > 4 files changed, 28 insertions(+), 33 deletions(-) > > > > diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/BmDma.c > > b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/BmDma.c > > index e8685666e79a..57e086a64dbc 100644 > > --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/BmDma.c > > +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/BmDma.c > > @@ -1,7 +1,7 @@ > > /** @file > > BmDma related function > > > > - Copyright (c) 2017, Intel Corporation. All rights reserved.
> > + Copyright (c) 2017 - 2018, Intel Corporation. All rights=20 > > + reserved.
> > This program and the accompanying materials > > are licensed and made available under the terms and conditions of=20 > > the BSD License > > which accompanies this distribution. The full text of the=20 > > license may be found at @@ -12,15 +12,7 @@ > > > > **/ > > > > -#include > > - > > -#include > > - > > -#include > > -#include > > -#include > > -#include -#include=20 > > > > +#include "DmaProtection.h" > > > > // TBD: May make it a policy > > #define DMA_MEMORY_TOP MAX_UINTN > > @@ -76,6 +68,7 @@ IoMmuMap ( > > MAP_INFO *MapInfo; > > EFI_PHYSICAL_ADDRESS > > DmaMemoryTop; > > BOOLEAN NeedRemap; > > + EFI_TPL OriginalTpl; > > > > if (NumberOfBytes =3D=3D NULL || DeviceAddress =3D=3D NULL || > > Mapping =3D=3D NULL) { > > @@ -198,7 +191,9 @@ IoMmuMap ( > > MapInfo->DeviceAddress =3D MapInfo->HostAddress; > > } > > > > + OriginalTpl =3D gBS->RaiseTPL (VTD_TPL_LEVEL); > > InsertTailList (&gMaps, &MapInfo->Link); > > + gBS->RestoreTPL (OriginalTpl); > > > > // > > // The DeviceAddress is the address of the maped buffer below 4GB=20 > > @@ -233,6 +228,7 @@ IoMmuUnmap ( { > > MAP_INFO *MapInfo; > > LIST_ENTRY *Link; > > + EFI_TPL OriginalTpl; > > > > DEBUG ((DEBUG_VERBOSE, "IoMmuUnmap: 0x%08x\n", Mapping)); > > > > @@ -241,6 +237,7 @@ IoMmuUnmap ( > > return EFI_INVALID_PARAMETER; > > } > > > > + OriginalTpl =3D gBS->RaiseTPL (VTD_TPL_LEVEL); > > MapInfo =3D NULL; > > for (Link =3D GetFirstNode (&gMaps) > > ; !IsNull (&gMaps, Link) > > @@ -255,10 +252,12 @@ IoMmuUnmap ( > > // Mapping is not a valid value returned by Map() > > // > > if (MapInfo !=3D Mapping) { > > + gBS->RestoreTPL (OriginalTpl); > > DEBUG ((DEBUG_ERROR, "IoMmuUnmap: %r\n",=20 > > EFI_INVALID_PARAMETER)); > > return EFI_INVALID_PARAMETER; > > } > > RemoveEntryList (&MapInfo->Link); > > + gBS->RestoreTPL (OriginalTpl); > > > > if (MapInfo->DeviceAddress !=3D MapInfo->HostAddress) { > > // > > diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c > > b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c > > index 648f64c20b77..013823cc161f 100644 > > --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c > > +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c > > @@ -478,7 +478,7 @@ InitializeDmaProtection ( > > > > Status =3D gBS->CreateEventEx ( > > EVT_NOTIFY_SIGNAL, > > - TPL_CALLBACK, > > + VTD_TPL_LEVEL, > > AcpiNotificationFunc, > > NULL, > > &gEfiAcpi10TableGuid, @@ -488,7 +488,7 @@=20 > > InitializeDmaProtection ( > > > > Status =3D gBS->CreateEventEx ( > > EVT_NOTIFY_SIGNAL, > > - TPL_CALLBACK, > > + VTD_TPL_LEVEL, > > AcpiNotificationFunc, > > NULL, > > &gEfiAcpi20TableGuid, @@ -505,7 +505,7 @@=20 > > InitializeDmaProtection ( > > > > Status =3D gBS->CreateEventEx ( > > EVT_NOTIFY_SIGNAL, > > - TPL_CALLBACK, > > + VTD_TPL_LEVEL, > > OnExitBootServices, > > NULL, > > &gEfiEventExitBootServicesGuid, @@ -514,7 +514,7=20 > > @@ InitializeDmaProtection ( > > ASSERT_EFI_ERROR (Status); > > > > Status =3D EfiCreateEventLegacyBootEx ( > > - TPL_CALLBACK, > > + VTD_TPL_LEVEL, > > OnLegacyBoot, > > NULL, > > &LegacyBootEvent > > diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h > > b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h > > index 519a5ab00450..bc14ff9a6631 100644 > > --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h > > +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h > > @@ -48,6 +48,8 @@ > > #define ALIGN_VALUE_UP(Value, Alignment) (((Value) + (Alignment) -=20 > > 1) & > > (~((Alignment) - 1))) > > #define ALIGN_VALUE_LOW(Value, Alignment) ((Value) & (~((Alignment)=20 > > - > 1))) > > > > +#define VTD_TPL_LEVEL TPL_NOTIFY > > + > > // > > // This is the initial max PCI DATA number. > > // The number may be enlarged later. > > diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c > > b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c > > index 89d9bea3fc0f..570b47cf7364 100644 > > --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c > > +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c > > @@ -12,16 +12,6 @@ > > > > **/ > > > > -#include > > - > > -#include > > -#include > > - > > -#include > > -#include > > -#include > > -#include > > - > > #include "DmaProtection.h" > > > > /** > > @@ -306,18 +296,22 @@ IoMmuSetAttribute ( > > EFI_STATUS Status; > > EFI_PHYSICAL_ADDRESS DeviceAddress; > > UINTN NumberOfPages; > > + EFI_TPL OriginalTpl; > > + > > + OriginalTpl =3D gBS->RaiseTPL (VTD_TPL_LEVEL); > > > > Status =3D GetDeviceInfoFromMapping (Mapping, &DeviceAddress,=20 > > &NumberOfPages); > > - if (EFI_ERROR(Status)) { > > - return Status; > > + if (!EFI_ERROR(Status)) { > > + Status =3D VTdSetAttribute ( > > + This, > > + DeviceHandle, > > + DeviceAddress, > > + EFI_PAGES_TO_SIZE(NumberOfPages), > > + IoMmuAccess > > + ); > > } > > - Status =3D VTdSetAttribute ( > > - This, > > - DeviceHandle, > > - DeviceAddress, > > - EFI_PAGES_TO_SIZE(NumberOfPages), > > - IoMmuAccess > > - ); > > + > > + gBS->RestoreTPL (OriginalTpl); > > > > return Status; > > } > > -- > > 2.7.0.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel