From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.88; helo=mga01.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F1FB322742A83 for ; Wed, 11 Apr 2018 22:37:47 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Apr 2018 22:37:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,440,1517904000"; d="scan'208";a="36610611" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga002.fm.intel.com with ESMTP; 11 Apr 2018 22:37:47 -0700 Received: from fmsmsx114.amr.corp.intel.com (10.18.116.8) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 11 Apr 2018 22:37:46 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX114.amr.corp.intel.com (10.18.116.8) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 11 Apr 2018 22:37:46 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.184]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.149]) with mapi id 14.03.0319.002; Thu, 12 Apr 2018 13:37:43 +0800 From: "Zeng, Star" To: "Wang, Jian J" , "edk2-devel@lists.01.org" CC: "Dong, Eric" , "Yao, Jiewen" , "Ni, Ruiyu" , "Kinney, Michael D" , "Zeng, Star" Thread-Topic: [PATCH v2] MdeModulePkg/PiSmmIpl: fix non-executable SMM RAM Thread-Index: AQHT0hrdauLdpB7QTU6EK90o2jKSkKP8nC2A Date: Thu, 12 Apr 2018 05:37:43 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103BAAC2E8@shsmsx102.ccr.corp.intel.com> References: <20180412045807.5060-1-jian.j.wang@intel.com> In-Reply-To: <20180412045807.5060-1-jian.j.wang@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2] MdeModulePkg/PiSmmIpl: fix non-executable SMM RAM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Apr 2018 05:37:48 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Has no need to set paging capability as the code is going to clear paging a= ttribute. With that refined, Reviewed-by: Star Zeng . Thanks, Star -----Original Message----- From: Wang, Jian J=20 Sent: Thursday, April 12, 2018 12:58 PM To: edk2-devel@lists.01.org Cc: Zeng, Star ; Dong, Eric ; Yao= , Jiewen ; Ni, Ruiyu ; Kinney, Mi= chael D Subject: [PATCH v2] MdeModulePkg/PiSmmIpl: fix non-executable SMM RAM > v2 changes: > a. Remove redundant code and fill-up potential logic hole > b. Code clean-up > c. Fix error in commit log This patch fixes an issue introduced by commit 5b91bf82c67b586b9588cbe4bbffa1588f6b5926 and 0c9f2cb10b7ddec56a3440e77219fd3ab1725e5c This issue will only happen if PcdDxeNxMemoryProtectionPolicy is enabled fo= r reserved memory, which will mark SMM RAM as NX (non- executable) during DXE core initialization. SMM IPL driver will unset the N= X attribute for SMM RAM to allow loading and running SMM core/drivers. But above commit will fail the unset operation of the NX attribute due to a= fact that SMM RAM has zero cache attribute (MRC code always sets 0 attribu= te to reserved memory), which will cause GCD internal method ConverToCpuArc= hAttributes() to return 0 attribute, which is taken as invalid CPU paging a= ttribute and skip the calling of gCpu->SetMemoryAttributes(). The solution is to make use of existing functionality in PiSmmIpl to make s= ure one cache attribute is set for SMM RAM. For performance consideration, = PiSmmIpl will always try to set SMM RAM to write-back. But there's a hole in the code which will fail the setting write-back attri= bute because of no corresponding cache capabilities. This patch will add ne= cessary cache capabilities before setting corresponding attributes. Cc: Star Zeng Cc: Eric Dong Cc: Jiewen Yao Cc: Ruiyu Ni Cc: Michael D Kinney Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang --- MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c | 51 ++++++++++++++++++++++++------= ---- 1 file changed, 37 insertions(+), 14 deletions(-) diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c b/MdeModulePkg/Core/PiS= mmCore/PiSmmIpl.c index 94d671bd74..dee6e62bf4 100644 --- a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c +++ b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c @@ -42,6 +42,15 @@ =20 #include "PiSmmCorePrivateData.h" =20 +#define SMRAM_CAPABILITIES \ + (EFI_MEMORY_WB | EFI_MEMORY_UC | EFI_MEMORY_XP | EFI_MEMORY_RP |=20 +EFI_MEMORY_RO) + +#define MEMORY_CACHE_ATTRIBUTES (EFI_MEMORY_UC | EFI_MEMORY_WC | \ + EFI_MEMORY_WT | EFI_MEMORY_WB | \ + EFI_MEMORY_WP | EFI_MEMORY_UCE) + +#define MEMORY_PAGE_ATTRIBUTES (EFI_MEMORY_XP | EFI_MEMORY_RP |=20 +EFI_MEMORY_RO) + // // Function prototypes from produced protocols // @@ -1617,34 +1626,48 @@= SmmIplEntry ( =20 GetSmramCacheRange (mCurrentSmramRange, &mSmramCacheBase, &mSmramCache= Size); // + // Make sure we can change the desired memory attributes. + // + Status =3D gDS->GetMemorySpaceDescriptor ( + mSmramCacheBase, + &MemDesc + ); + ASSERT_EFI_ERROR (Status); + if ((MemDesc.Capabilities & SMRAM_CAPABILITIES) !=3D SMRAM_CAPABILITIE= S) { + gDS->SetMemorySpaceCapabilities ( + mSmramCacheBase, + mSmramCacheSize, + MemDesc.Capabilities | SMRAM_CAPABILITIES + ); + } + // // If CPU AP is present, attempt to set SMRAM cacheability to WB and c= lear - // XP if it's set. + // all paging attributes. // Note that it is expected that cacheability of SMRAM has been set to= WB if CPU AP // is not available here. // CpuArch =3D NULL; Status =3D gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID = **)&CpuArch); if (!EFI_ERROR (Status)) { - Status =3D gDS->SetMemorySpaceAttributes( - mSmramCacheBase,=20 + MemDesc.Attributes &=3D ~(MEMORY_CACHE_ATTRIBUTES | MEMORY_PAGE_ATTR= IBUTES); + MemDesc.Attributes |=3D EFI_MEMORY_WB; + Status =3D gDS->SetMemorySpaceAttributes ( + mSmramCacheBase, mSmramCacheSize, - EFI_MEMORY_WB + MemDesc.Attributes ); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_WARN, "SMM IPL failed to set SMRAM window to EFI_MEM= ORY_WB\n")); } =20 - Status =3D gDS->GetMemorySpaceDescriptor( - mCurrentSmramRange->PhysicalStart, - &MemDesc - ); - if (!EFI_ERROR (Status) && (MemDesc.Attributes & EFI_MEMORY_XP) !=3D= 0) { - gDS->SetMemorySpaceAttributes ( - mCurrentSmramRange->PhysicalStart, - mCurrentSmramRange->PhysicalSize, - MemDesc.Attributes & (~EFI_MEMORY_XP) + DEBUG_CODE ( + gDS->GetMemorySpaceDescriptor ( + mSmramCacheBase, + &MemDesc ); - } + DEBUG ((DEBUG_INFO, "SMRAM attributes: %016lx\n", MemDesc.Attribut= es)); + ASSERT ((MemDesc.Attributes & MEMORY_PAGE_ATTRIBUTES) =3D=3D 0); + ); } // // if Loading module at Fixed Address feature is enabled, save the SMR= AM base to Load -- 2.16.2.windows.1