From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C32AF207E36C6 for ; Wed, 23 May 2018 00:30:29 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 May 2018 00:30:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,432,1520924400"; d="scan'208";a="51478143" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by FMSMGA003.fm.intel.com with ESMTP; 23 May 2018 00:30:28 -0700 Received: from fmsmsx121.amr.corp.intel.com (10.18.125.36) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 23 May 2018 00:30:28 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx121.amr.corp.intel.com (10.18.125.36) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 23 May 2018 00:30:28 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.79]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.210]) with mapi id 14.03.0319.002; Wed, 23 May 2018 15:30:27 +0800 From: "Zeng, Star" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" CC: "Zeng, Star" Thread-Topic: [PATCH] MdeModulePkg/PciBus: Use actual max bus # for subordinary bus # Thread-Index: AQHT8kZEMi+kP1vbxkuoArduYzj7yKQ86ttQ Date: Wed, 23 May 2018 07:30:27 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103BAEE90E@shsmsx102.ccr.corp.intel.com> References: <20180523032931.183708-1-ruiyu.ni@intel.com> In-Reply-To: <20180523032931.183708-1-ruiyu.ni@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdeModulePkg/PciBus: Use actual max bus # for subordinary bus # X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 May 2018 07:30:30 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable The code comment "// Get next available PCI bus number" comes from PciAlloc= ateBusNumber? It should be updated accordingly for PciGetMaxBusNumber, right? With the comment updated, Reviewed-by: Star Zeng . Thanks, Star -----Original Message----- From: Ni, Ruiyu=20 Sent: Wednesday, May 23, 2018 11:30 AM To: edk2-devel@lists.01.org Cc: Zeng, Star Subject: [PATCH] MdeModulePkg/PciBus: Use actual max bus # for subordinary = bus # Current code assumes the max bus(0xFF) is under this P2P bridge and tempora= rily set it as subordinate bus. It may cause silicon hangs during PCI enumeration in some specific case. Instead, it should get the max bus number from the bus number resources ret= urned from PCI_HOST_BRIDGE_RESOURCE_ALLOCATION.StartBusEnumeration() and set it as sub= ordinate bus. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Star Zeng --- MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c | 39 +++++++++++++++++++++++++++++= +++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciLib.c index 976496379a..729e86b55e 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c @@ -29,6 +29,43 @@ CHAR16 *mBarTypeStr[] =3D { L"Unknow" }; =20 +/** + Retrieve the max bus number that is assigned to the Root Bridge hierarch= y. + It can support the case that there are multiple bus ranges. + + @param Bridge Bridge device instance. + + @retval The max bus number that is assigned to this Roo= t Bridge hierarchy. + +**/ +UINT16 +PciGetMaxBusNumber ( + IN PCI_IO_DEVICE *Bridge + ) +{ + PCI_IO_DEVICE *RootBridge; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *BusNumberRanges; + UINT64 MaxNumberInRange; + + // + // Get PCI Root Bridge device + // + RootBridge =3D Bridge; + while (RootBridge->Parent !=3D NULL) { + RootBridge =3D RootBridge->Parent; + } + MaxNumberInRange =3D 0; + // + // Get next available PCI bus number + // + BusNumberRanges =3D RootBridge->BusNumberRanges; + while (BusNumberRanges->Desc !=3D ACPI_END_TAG_DESCRIPTOR) { + MaxNumberInRange =3D BusNumberRanges->AddrRangeMin + BusNumberRanges->= AddrLen - 1; + BusNumberRanges++; + } + return (UINT16) MaxNumberInRange; +} + /** Retrieve the PCI Card device BAR information via PciIo interface. =20 @@ -1193,7 +1230,7 @@ PciScanBus ( // Temporarily initialize SubBusNumber to maximum bus number to = ensure the // PCI configuration transaction to go through any PPB // - Register =3D 0xFF; + Register =3D PciGetMaxBusNumber (Bridge); Address =3D EFI_PCI_ADDRESS (StartBusNumber, Device, Func, PCI= _BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET); Status =3D PciRootBridgeIo->Pci.Write ( PciRootBridgeIo, -- 2.16.1.windows.1