From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 70FC3203B9909 for ; Fri, 25 May 2018 02:06:24 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 May 2018 02:06:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,439,1520924400"; d="scan'208";a="231729737" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga006.fm.intel.com with ESMTP; 25 May 2018 02:06:24 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 25 May 2018 02:06:23 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.79]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.17]) with mapi id 14.03.0319.002; Fri, 25 May 2018 17:06:14 +0800 From: "Zeng, Star" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" CC: "Zeng, Star" Thread-Topic: [PATCH] PcAtChipsetPkg/PcRtc: Add two new PCD for RTC Index/Target registers Thread-Index: AQHT9ATMvJz6KK5D0EGEioy3EovolqRAJVww Date: Fri, 25 May 2018 09:06:14 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103BAF109E@shsmsx102.ccr.corp.intel.com> References: <20180525084556.305832-1-ruiyu.ni@intel.com> In-Reply-To: <20180525084556.305832-1-ruiyu.ni@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] PcAtChipsetPkg/PcRtc: Add two new PCD for RTC Index/Target registers X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 May 2018 09:06:25 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Two minor comments: 1. PcAtChipsetPkg.uni also needs to be updated for the new PCDs. 2. Update all the places of the two macros, or just update like below? Just= for you to consider. :) I do not insist. #define PCAT_RTC_ADDRESS_REGISTER PcdGet8 (PcdRtcIndexRegister) #define PCAT_RTC_DATA_REGISTER PcdGet8 (PcdRtcTargetRegister)) Thanks, Star -----Original Message----- From: Ni, Ruiyu=20 Sent: Friday, May 25, 2018 4:46 PM To: edk2-devel@lists.01.org Cc: Zeng, Star Subject: [PATCH] PcAtChipsetPkg/PcRtc: Add two new PCD for RTC Index/Target= registers In certain HW implementation, the BIT7 of RTC Index register(0x70) is for NMI sources enable/disable but the BIT7 of 0x70 cannot be read before writing. Software which doesn't want to change the NMI sources enable/disable setting can write to the alias register 0x74, through which only BIT0 ~ BIT6 of 0x70 is modified. So two new PCDs are added so that platform can have the flexibility to change the default RTC register addresses from 0x70/0x71 to 0x74/0x75. With the new PCDs added, it can also support special HW that provides RTC storage in a different register pairs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni Cc: Star Zeng --- PcAtChipsetPkg/PcAtChipsetPkg.dec | 10 ++++++= +++- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c | 10 +++++-= ---- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h | 5 +---- .../PcatRealTimeClockRuntimeDxe.inf | 4 +++- 4 files changed, 18 insertions(+), 11 deletions(-) diff --git a/PcAtChipsetPkg/PcAtChipsetPkg.dec b/PcAtChipsetPkg/PcAtChipset= Pkg.dec index f11d2045a4..ace7fb7e88 100644 --- a/PcAtChipsetPkg/PcAtChipsetPkg.dec +++ b/PcAtChipsetPkg/PcAtChipsetPkg.dec @@ -4,7 +4,7 @@ # This package is designed to public interfaces and implementation which f= ollows # PcAt defacto standard. # -# Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Inc. All rights reserved.
# # This program and the accompanying materials @@ -194,5 +194,13 @@ [PcdsFixedAtBuild, PcdsPatchableInModule] # @Prompt Initial value for Register_D in RTC. gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD|0x00|UINT8|0x0= 000001D =20 + ## Specifies RTC Index Register address in I/O space. + # @Prompt RTC Index Register address + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x70|UINT8|0x0000001E + + ## Specifies RTC Target Register address in I/O space. + # @Prompt RTC Target Register address + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x71|UINT8|0x0000001F + [UserExtensions.TianoCore."ExtraFiles"] PcAtChipsetPkgExtra.uni diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c b/PcAtChips= etPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c index c032e16217..caecd0ac1e 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c @@ -1,7 +1,7 @@ /** @file RTC Architectural Protocol GUID as defined in DxeCis 0.96. =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Inc. All rights reserved.
=20 This program and the accompanying materials @@ -72,8 +72,8 @@ RtcRead ( IN UINT8 Address ) { - IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, (UINT8) (Address | (UINT8) (IoRead8= (PCAT_RTC_ADDRESS_REGISTER) & 0x80))); - return IoRead8 (PCAT_RTC_DATA_REGISTER); + IoWrite8 (PcdGet8 (PcdRtcIndexRegister), (UINT8) (Address | (UINT8) (IoR= ead8 (PcdGet8 (PcdRtcIndexRegister)) & 0x80))); + return IoRead8 (PcdGet8 (PcdRtcTargetRegister)); } =20 /** @@ -90,8 +90,8 @@ RtcWrite ( IN UINT8 Data ) { - IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, (UINT8) (Address | (UINT8) (IoRead8= (PCAT_RTC_ADDRESS_REGISTER) & 0x80))); - IoWrite8 (PCAT_RTC_DATA_REGISTER, Data); + IoWrite8 (PcdGet8 (PcdRtcIndexRegister), (UINT8) (Address | (UINT8) (IoR= ead8 (PcdGet8 (PcdRtcIndexRegister)) & 0x80))); + IoWrite8 (PcdGet8 (PcdRtcTargetRegister), Data); } =20 /** diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h b/PcAtChips= etPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h index 8aeb12c88a..3b68f8cc9e 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h @@ -1,7 +1,7 @@ /** @file Header file for real time clock driver. =20 -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Inc. All rights reserved.
=20 This program and the accompanying materials @@ -47,9 +47,6 @@ typedef struct { =20 extern PC_RTC_MODULE_GLOBALS mModuleGlobal; =20 -#define PCAT_RTC_ADDRESS_REGISTER 0x70 -#define PCAT_RTC_DATA_REGISTER 0x71 - // // Dallas DS12C887 Real Time Clock // diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRu= ntimeDxe.inf b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClock= RuntimeDxe.inf index 1b2b063623..4d1360744d 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDx= e.inf +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDx= e.inf @@ -4,7 +4,7 @@ # This driver provides GetTime, SetTime, GetWakeupTime, SetWakeupTime serv= ices to Runtime Service Table. # It will install a tagging protocol with gEfiRealTimeClockArchProtocolGui= d. # -# Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Inc. All rights reserved.
# # This program and the accompanying materials @@ -77,6 +77,8 @@ [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout ## CONSUME= S gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear ## CONSUME= S gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear ## CONSUME= S + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister ## CONSUME= S + gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister ## CONSUME= S =20 [Depex] gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid --=20 2.16.1.windows.1