From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E34B1211799E4 for ; Wed, 6 Jun 2018 02:07:35 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Jun 2018 02:07:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,482,1520924400"; d="scan'208";a="46823827" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga007.jf.intel.com with ESMTP; 06 Jun 2018 02:07:34 -0700 Received: from fmsmsx126.amr.corp.intel.com (10.18.125.43) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 6 Jun 2018 02:07:08 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX126.amr.corp.intel.com (10.18.125.43) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 6 Jun 2018 02:07:07 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.223]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.70]) with mapi id 14.03.0319.002; Wed, 6 Jun 2018 17:07:05 +0800 From: "Zeng, Star" To: "Duran, Leo" , "Dong, Eric" CC: "edk2-devel@lists.01.org" , "Zeng, Star" Thread-Topic: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode Thread-Index: AQHT85KFbSIpfcpq/ECPOM2elVP7P6RASzXQ//+i2gCAEcrygIAAvl5g//+AKYCAAQuhgA== Date: Wed, 6 Jun 2018 09:07:05 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103BB54038@shsmsx102.ccr.corp.intel.com> References: <1527188850-4553-1-git-send-email-leo.duran@amd.com> <1527188850-4553-2-git-send-email-leo.duran@amd.com>, <0C09AFA07DD0434D9E2A0C6AEB0483103BAF1160@shsmsx102.ccr.corp.intel.com> <0C09AFA07DD0434D9E2A0C6AEB0483103BB53B9A@shsmsx102.ccr.corp.intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: Ensure FIFO Polled Mode X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jun 2018 09:07:36 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Leo, I am ok with the code change. I was just curious about the motivation for the change. 1. No real issue met, but just to follow the doc 8.4.2 ? 2. Real issue met, then what is the issue ? 3. What is the default value of IER for your case ? If the information are valuable, then they can be added into the commit mes= sage for further easy maintenance. -----Original Message----- From: Duran, Leo [mailto:leo.duran@amd.com]=20 Sent: Wednesday, June 6, 2018 9:05 AM To: Zeng, Star ; Dong, Eric Cc: edk2-devel@lists.01.org Subject: RE: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: En= sure FIFO Polled Mode Hi Star, I came across a 16550 model (simulation) which required clearing IER, and i= t seems that's allowed in the 16650 spec, as noted here: http://www.ti.com/lit/ds/symlink/pc16550d.pdf 8.4.2 FIFO Polled Mode Operation With FCR0=3D1 resetting IER0, IER1, IER2, IER3 or all to zero puts the UART= in the FIFO Polled Mode of operation. Thanks, Leo. > -----Original Message----- > From: Zeng, Star [mailto:star.zeng@intel.com] > Sent: Tuesday, June 05, 2018 7:43 PM > To: Duran, Leo ; Dong, Eric > Cc: edk2-devel@lists.01.org; Zeng, Star > Subject: RE: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode >=20 > It will be better to have the information that may could be added into=20 > the commit message. >=20 > 1. Did you meet real issue without this patch? > 2. what is the default value of IER in your case? >=20 >=20 > Thanks, > Star > -----Original Message----- > From: Duran, Leo [mailto:leo.duran@amd.com] > Sent: Wednesday, June 6, 2018 5:21 AM > To: Zeng, Star ; Dong, Eric > Cc: edk2-devel@lists.01.org > Subject: RE: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode >=20 > Any updates on this patch? >=20 > Do you require to know my "default value of IER"? >=20 > Thanks, > Leo. >=20 > -----Original Message----- > From: edk2-devel On Behalf Of Duran,=20 > Leo > Sent: Friday, May 25, 2018 8:38 AM > To: Zeng, Star ; edk2-devel@lists.01.org > Cc: Dong, Eric ; Zeng, Star > Subject: Re: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode >=20 > Don''t have access to test platform at this time. > But will report IER value if I,m able to. >=20 > Leo >=20 > Get Outlook for iOS=20 > ________________________________ > From: Zeng, Star > Sent: Friday, May 25, 2018 6:13:16 AM > To: Duran, Leo; edk2-devel@lists.01.org > Cc: Dong, Eric; Zeng, Star > Subject: RE: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode >=20 > Reviewed-by: Star Zeng >=20 > Just a little curious about > 1. Did you meet real issue without this patch? > 2. what is the default value of IER in your case? >=20 >=20 > Thanks, > Star > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of=20 > Leo Duran > Sent: Friday, May 25, 2018 3:08 AM > To: edk2-devel@lists.01.org > Cc: Dong, Eric ; Zeng, Star > Subject: [edk2] [PATCH] MdeModulePkg/Library/BaseSerialPortLib16550: > Ensure FIFO Polled Mode >=20 > Put the UART in FIFO Polled Mode by clearing IER after setting FCR. > Also, add comments to show DLAB state for registers 0 and 1. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Leo Duran > Cc: Star Zeng > CC: Eric Dong > --- > .../BaseSerialPortLib16550/BaseSerialPortLib16550.c | 16 ++++++++++= ++-- > -- > 1 file changed, 12 insertions(+), 4 deletions(-) >=20 > diff --git > a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > index 0ccac96..6532c4d 100644 > --- > a/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.c > +++ > b/MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550 > +++ .c > @@ -3,6 +3,8 @@ >=20 > (C) Copyright 2014 Hewlett-Packard Development Company, L.P.
> Copyright (c) 2006 - 2016, Intel Corporation. All rights=20 > reserved.
> + Copyright (c) 2018, AMD Incorporated. All rights reserved.
> + > This program and the accompanying materials > are licensed and made available under the terms and conditions of=20 > the BSD License > which accompanies this distribution. The full text of the license=20 > may be found at @@ -30,10 +32,11 @@ // // 16550 UART register=20 > offsets and bitfields // > -#define R_UART_RXBUF 0 > -#define R_UART_TXBUF 0 > -#define R_UART_BAUD_LOW 0 > -#define R_UART_BAUD_HIGH 1 > +#define R_UART_RXBUF 0 // LCR_DLAB =3D 0 > +#define R_UART_TXBUF 0 // LCR_DLAB =3D 0 > +#define R_UART_BAUD_LOW 0 // LCR_DLAB =3D 1 > +#define R_UART_BAUD_HIGH 1 // LCR_DLAB =3D 1 > +#define R_UART_IER 1 // LCR_DLAB =3D 0 > #define R_UART_FCR 2 > #define B_UART_FCR_FIFOE BIT0 > #define B_UART_FCR_FIFO64 BIT5 > @@ -554,6 +557,11 @@ SerialPortInitialize ( > SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, > (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE |=20 > B_UART_FCR_FIFO64))); >=20 > // > + // Set FIFO Polled Mode by clearing IER after setting FCR //=20 > + SerialPortWriteRegister (SerialRegisterBase, R_UART_IER, 0x00); > + > + // > // Put Modem Control Register(MCR) into its reset state of 0x00. > // > SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00); > -- > 2.7.4 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel