From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1AD0D207E36C6 for ; Thu, 7 Jun 2018 19:54:01 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Jun 2018 19:54:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,489,1520924400"; d="scan'208";a="48227992" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga006.jf.intel.com with ESMTP; 07 Jun 2018 19:54:01 -0700 Received: from fmsmsx151.amr.corp.intel.com (10.18.125.4) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 7 Jun 2018 19:54:00 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX151.amr.corp.intel.com (10.18.125.4) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 7 Jun 2018 19:53:53 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.223]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.51]) with mapi id 14.03.0319.002; Fri, 8 Jun 2018 10:53:52 +0800 From: "Zeng, Star" To: Ard Biesheuvel , "edk2-devel@lists.01.org" CC: "leif.lindholm@linaro.org" , "Kinney, Michael D" , "Yao, Jiewen" , "Zeng, Star" Thread-Topic: [PATCH 1/5] MdeModulePkg/CapsulePei: clean Dcache before consuming capsule data Thread-Index: AQHT/k/YXbpMFZ6XjUK0LykNMTS7YaRVquHg Date: Fri, 8 Jun 2018 02:53:51 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103BB54B3F@shsmsx102.ccr.corp.intel.com> References: <20180607110812.26778-1-ard.biesheuvel@linaro.org> <20180607110812.26778-2-ard.biesheuvel@linaro.org> In-Reply-To: <20180607110812.26778-2-ard.biesheuvel@linaro.org> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 1/5] MdeModulePkg/CapsulePei: clean Dcache before consuming capsule data X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jun 2018 02:54:02 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable I suggest to use goto/adjust code to have one place for both paths to perfo= rm cache maintenance (with comments). Thanks, Star -----Original Message----- From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org]=20 Sent: Thursday, June 7, 2018 7:08 PM To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org; Kinney, Michael D ; Yao, Jiewen ; Zeng, Star ; Ar= d Biesheuvel Subject: [PATCH 1/5] MdeModulePkg/CapsulePei: clean Dcache before consuming= capsule data When capsule updates are staged for processing after a warm reboot, they ar= e copied into memory with the MMU and caches enabled. When the capsule PEI = gets around to coalescing the capsule, the MMU and caches may still be disa= bled, and so on architectures where uncached accesses are incoherent with t= he caches (such as ARM and AARCH64), we may read stale data if we don't cle= an the caches to memory first. Note that this cache maintenance cannot be done during the invocation of Up= dateCapsule(), since the ScatterGatherList structures are only identified b= y physical address, and at runtime, the firmware doesn't know whether and w= here this memory is mapped, and cache maintenance requires a virtual addres= s. Reviewed-by: Jiewen Yao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- MdeModulePkg/Universal/CapsulePei/CapsulePei.inf | 1 + MdeModulePkg/Universal/CapsulePei/Common/CapsuleCoalesce.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf b/MdeModulePk= g/Universal/CapsulePei/CapsulePei.inf index c54bc21a95a8..594e110d1f8a 100644 --- a/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf +++ b/MdeModulePkg/Universal/CapsulePei/CapsulePei.inf @@ -48,6 +48,7 @@ [Packages] =20 [LibraryClasses] BaseLib + CacheMaintenanceLib HobLib BaseMemoryLib PeiServicesLib diff --git a/MdeModulePkg/Universal/CapsulePei/Common/CapsuleCoalesce.c b/M= deModulePkg/Universal/CapsulePei/Common/CapsuleCoalesce.c index 3e7054cd38a9..fb59f338f100 100644 --- a/MdeModulePkg/Universal/CapsulePei/Common/CapsuleCoalesce.c +++ b/MdeModulePkg/Universal/CapsulePei/Common/CapsuleCoalesce.c @@ -27,6 +27,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include =20 #include +#include #include #include #include @@ -274,6 +275,7 @@ ValidateCapsuleByMemoryResource ( // // No memory resource descriptor reported in HOB list before capsule C= oalesce. // + WriteBackDataCacheRange ((VOID *)(UINTN)Address, (UINTN)Size); return TRUE; } =20 @@ -283,6 +285,14 @@ ValidateCapsuleByMemoryResource ( DEBUG ((EFI_D_INFO, "Address(0x%lx) Size(0x%lx) in MemoryResource[0x= %x] - Start(0x%lx) Length(0x%lx)\n", Address, Size, Index, MemoryResource[Index].PhysicalStart, Memo= ryResource[Index].ResourceLength)); + + // + // At this point, we may still be running with the MMU and caches di= sabled, + // and on architectures such as ARM or AARCH64, capsule [meta]data l= oaded + // into memory with the caches on is only guaranteed to be visible t= o the + // CPU running with the caches off after performing an explicit writ= eback. + // + WriteBackDataCacheRange ((VOID *)(UINTN)Address, (UINTN)Size); return TRUE; } } -- 2.17.0