From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=star.zeng@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9178721159CBC for ; Thu, 27 Sep 2018 19:43:36 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Sep 2018 19:43:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,313,1534834800"; d="scan'208";a="87407412" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga003.jf.intel.com with ESMTP; 27 Sep 2018 19:38:59 -0700 Received: from fmsmsx126.amr.corp.intel.com (10.18.125.43) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 27 Sep 2018 19:38:58 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by FMSMSX126.amr.corp.intel.com (10.18.125.43) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 27 Sep 2018 19:38:58 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.140]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.220]) with mapi id 14.03.0319.002; Fri, 28 Sep 2018 10:38:56 +0800 From: "Zeng, Star" To: "Chiu, Chasel" , "edk2-devel@lists.01.org" CC: "Yao, Jiewen" , "Zeng, Star" Thread-Topic: [edk2] [PATCH] IntelFsp2(Wrapper)Pkg: Revert from e8208100 to 737f812b Thread-Index: AQHUVtRPobA5A3A14UeWl+jkBS7HEqUE+w9Q Date: Fri, 28 Sep 2018 02:38:55 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483103BBF46D0@shsmsx102.ccr.corp.intel.com> References: <20180928023751.15220-1-chasel.chiu@intel.com> In-Reply-To: <20180928023751.15220-1-chasel.chiu@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] IntelFsp2(Wrapper)Pkg: Revert from e8208100 to 737f812b X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Sep 2018 02:43:36 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Star Zeng -----Original Message----- From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Chas= el, Chiu Sent: Friday, September 28, 2018 10:38 AM To: edk2-devel@lists.01.org Cc: Yao, Jiewen ; Zeng, Star Subject: [edk2] [PATCH] IntelFsp2(Wrapper)Pkg: Revert from e8208100 to 737f= 812b Commit formats had issues so reverted 9 commits from IntelFsp2Pkg and IntelFsp2WrapperPkg. Will re-submit them with correct formats. Cc: Jiewen Yao Cc: Star Zeng Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 6 ++ IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf | 11 +++ IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf | 5 ++ .../Library/BaseFspCommonLib/BaseFspCommonLib.inf | 5 ++ .../BaseFspPlatformLib/BaseFspPlatformLib.inf | 9 +++ .../BaseFspSwitchStackLib.inf | 4 ++ IntelFsp2Pkg/Tools/GenCfgOpt.py | 83 ++----------------= ---- .../FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf | 1 + .../BaseFspWrapperPlatformLibSample.inf | 3 + 9 files changed, 51 insertions(+), 76 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf b/IntelFsp2Pkg/FspSecC= ore/FspSecCoreM.inf index c657862deb..0500a197f8 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf @@ -58,11 +58,17 @@ FspSecPlatformLib =20 [Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## UNDEFINED + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES =20 +[FixedPcd] + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES + [Ppis] gEfiTemporaryRamSupportPpiGuid ## PRODUCES =20 diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf b/IntelFsp2Pkg/FspSecC= ore/FspSecCoreS.inf index dd3f8e56a0..a3563dd8cf 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf @@ -52,6 +52,17 @@ FspCommonLib FspSecPlatformLib =20 +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## UNDEFINED + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES + +[FixedPcd] + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES + [Ppis] gEfiTemporaryRamSupportPpiGuid ## PRODUCES =20 diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf b/IntelFsp2Pkg/FspSecC= ore/FspSecCoreT.inf index aff4b23f88..cf6a1918a3 100644 --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf @@ -53,9 +53,14 @@ FspSecPlatformLib =20 [Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## UNDEFINED gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES =20 +[FixedPcd] + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES + [Ppis] gEfiTemporaryRamSupportPpiGuid ## PRODUCES diff --git a/IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf b/I= ntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf index ff82f8040b..c9d98357e2 100644 --- a/IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf +++ b/IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf @@ -33,3 +33,8 @@ [Pcd] gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES =20 +[FixedPcd] + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES diff --git a/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf= b/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf index b9e8a61809..907482daed 100644 --- a/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf +++ b/IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf @@ -35,6 +35,12 @@ PerformanceLib ReportStatusCodeLib =20 +[Pcd] + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES + [Guids] gFspPerformanceDataGuid ## CONSUMES ##= GUID gFspEventEndOfFirmwareGuid ## PRODUCES ##= GUID @@ -43,3 +49,6 @@ [Protocols] gEfiPciEnumerationCompleteProtocolGuid ## CONSUMES =20 +[FixedPcd] + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackL= ib.inf b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.i= nf index 97cf3caa6a..b3c673a0ac 100644 --- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf +++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf @@ -34,5 +34,9 @@ BaseLib IoLib =20 +[FixedPcd] + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPatchEntry ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxPerfEntry ## CONSUMES + =20 =20 diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt= .py index 059cfcb7e4..c9b7bc5373 100644 --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py @@ -1,6 +1,6 @@ ## @ GenCfgOpt.py # -# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
# This program and the accompanying materials are licensed and made availa= ble under # the terms and conditions of the BSD License that accompanies this distri= bution. # The full text of the license may be found at @@ -418,8 +418,6 @@ EndList return "" =20 def ParseDscFile (self, DscFile, FvDir): - Hardcode =3D False - AutoAlign =3D False self._CfgItemList =3D [] self._CfgPageDict =3D {} self._CfgBlkDict =3D {} @@ -440,8 +438,6 @@ EndList DscLines =3D DscFd.readlines() DscFd.close() =20 - MaxAlign =3D 32 #Default align to 32, but if there are 64 bit un= it, align to 64 - SizeAlign =3D 0 #record the struct max align while len(DscLines): DscLine =3D DscLines.pop(0).strip() Handle =3D False @@ -453,7 +449,7 @@ EndList IsUpdSect =3D False if Match.group(1).lower() =3D=3D "Defines".lower(): IsDefSect =3D True - if (Match.group(1).lower() =3D=3D "PcdsFeatureFlag".lower= () or Match.group(1).lower() =3D=3D "PcdsFixedAtBuild".lower()): + if Match.group(1).lower() =3D=3D "PcdsFeatureFlag".lower(= ): IsPcdSect =3D True elif Match.group(1).lower() =3D=3D "PcdsDynamicVpd.Upd".lo= wer(): ConfigDict =3D {} @@ -468,7 +464,6 @@ EndList ConfigDict['comment'] =3D '' ConfigDict['subreg'] =3D [] IsUpdSect =3D True - Offset =3D 0 else: if IsDefSect or IsPcdSect or IsUpdSect or IsVpdSect: if re.match("^!else($|\s+#.+)", DscLine): @@ -496,7 +491,7 @@ EndList IfStack.append(Result) ElifStack.append(0) else: - Match =3D re.match("!(if|elseif)\s+(.+)", Dsc= Line.split("#")[0]) + Match =3D re.match("!(if|elseif)\s+(.+)", Dsc= Line) if Match: Result =3D self.EvaluateExpress(Match.grou= p(2)) if Match.group(1) =3D=3D "if": @@ -535,7 +530,6 @@ EndList NewDscLines =3D IncludeDsc.readlin= es() IncludeDsc.close() DscLines =3D NewDscLines + DscLine= s - Offset =3D 0 else: if DscLine.startswith('!'): print("ERROR: Unrecoginized di= rective for line '%s'" % DscLine) @@ -626,22 +620,13 @@ EndList =20 # Check VPD/UPD if IsUpdSect: - Match =3D re.match("^([_a-zA-Z0-9]+).([_a-zA-Z0-9]+)\s= *\|\s*(0x[0-9A-F]+|\*)\s*\|\s*(\d+|0x[0-9a-fA-F]+)\s*\|\s*(.+)",DscLine) + Match =3D re.match("^([_a-zA-Z0-9]+).([_a-zA-Z0-9]+)\s= *\|\s*(0x[0-9A-F]+)\s*\|\s*(\d+|0x[0-9a-fA-F]+)\s*\|\s*(.+)",DscLine) else: Match =3D re.match("^([_a-zA-Z0-9]+).([_a-zA-Z0-9]+)\s= *\|\s*(0x[0-9A-F]+)(?:\s*\|\s*(.+))?", DscLine) if Match: ConfigDict['space'] =3D Match.group(1) ConfigDict['cname'] =3D Match.group(2) - if Match.group(3) !=3D '*': - Hardcode =3D True - Offset =3D int (Match.group(3), 16) - else: - AutoAlign =3D True - - if Hardcode and AutoAlign: - print("Hardcode and auto-align mixed mode is not s= upported by GenCfgOpt") - raise SystemExit - ConfigDict['offset'] =3D Offset + ConfigDict['offset'] =3D int (Match.group(3), 16) if ConfigDict['order'] =3D=3D -1: ConfigDict['order'] =3D ConfigDict['offset'] << 8 else: @@ -653,7 +638,6 @@ EndList Length =3D int (Match.group(4), 16) else : Length =3D int (Match.group(4)) - Offset +=3D Length else: Value =3D Match.group(4) if Value is None: @@ -681,52 +665,6 @@ EndList ConfigDict['help'] =3D '' ConfigDict['type'] =3D '' ConfigDict['option'] =3D '' - if IsUpdSect and AutoAlign: - ItemLength =3D int(ConfigDict['length']) - ItemOffset =3D int(ConfigDict['offset']) - ItemStruct =3D ConfigDict['struct'] - Unit =3D 1 - if ItemLength in [1, 2, 4, 8] and not ConfigDict['= value'].startswith('{'): - Unit =3D ItemLength - # If there are 64 bit unit, align to 64 - if Unit =3D=3D 8: - MaxAlign =3D 64 - SizeAlign =3D 8 - if ItemStruct !=3D '': - UnitDict =3D {'UINT8':1, 'UINT16':2, 'UINT32':= 4, 'UINT64':8} - if ItemStruct in ['UINT8', 'UINT16', 'UINT32',= 'UINT64']: - Unit =3D UnitDict[ItemStruct] - # If there are 64 bit unit, align to 64 - if Unit =3D=3D 8: - MaxAlign =3D 64 - SizeAlign =3D max(SizeAlign, Unit) - if (ConfigDict['embed'].find(':START') !=3D -1): - Base =3D ItemOffset - SubOffset =3D ItemOffset - Base - SubRemainder =3D SubOffset % Unit - if SubRemainder: - Diff =3D Unit - SubRemainder - Offset =3D Offset + Diff - ItemOffset =3D ItemOffset + Diff - - if (ConfigDict['embed'].find(':END') !=3D -1): - Remainder =3D Offset % (MaxAlign/8) # MaxAli= gn is either 32 or 64 - if Remainder: - Diff =3D (MaxAlign/8) - Remainder - Offset =3D Offset + Diff - ItemOffset =3D ItemOffset + Diff - MaxAlign =3D 32 # Reset = to default 32 align when struct end - if (ConfigDict['cname'] =3D=3D 'UpdTerminator'): - # ItemLength is the size of UpdTerminator - # Itemlength might be 16, 32, or 64 - # Struct align to 64 if UpdTerminator - # or struct size is 64 bit, else align to 32 - Remainder =3D Offset % max(ItemLength/8, 4, Si= zeAlign) - Offset =3D Offset + ItemLength - if Remainder: - Diff =3D max(ItemLength/8, 4, SizeAlign) -= Remainder - ItemOffset =3D ItemOffset + Diff - ConfigDict['offset'] =3D ItemOffset =20 self._CfgItemList.append(ConfigDict.copy()) ConfigDict['name'] =3D '' @@ -1038,13 +976,6 @@ EndList NewTextBody.extend(OldTextBody) return NewTextBody =20 - def WriteLinesWithoutTailingSpace (self, HeaderFd, Line): - TxtBody2 =3D Line.splitlines(True) - for Line2 in TxtBody2: - Line2 =3D Line2.rstrip() - Line2 +=3D '\n' - HeaderFd.write (Line2) - return 0 def CreateHeaderFile (self, InputHeaderFile): FvDir =3D self._FvDir =20 @@ -1244,7 +1175,7 @@ EndList Index +=3D 1 for Item in range(len(StructStart)): if Index >=3D StructStartWithComment[Item] and Index <= =3D StructEnd[Item]: - self.WriteLinesWithoutTailingSpace(HeaderFd, Line) + HeaderFd.write (Line) HeaderFd.write("#pragma pack()\n\n") HeaderFd.write("#endif\n") HeaderFd.close() @@ -1289,7 +1220,7 @@ EndList Index +=3D 1 for Item in range(len(StructStart)): if Index >=3D StructStartWithComment[Item] and Index <= =3D StructEnd[Item]: - self.WriteLinesWithoutTailingSpace(HeaderFd, Line) + HeaderFd.write (Line) HeaderFd.write("#pragma pack()\n\n") HeaderFd.write("#endif\n") HeaderFd.close() diff --git a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.in= f b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf index 011cf89d3f..ce3bfa0c75 100644 --- a/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf +++ b/IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf @@ -61,6 +61,7 @@ gFspHobGuid ## CONSUMES ## HOB =20 [Pcd] + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdSkipFspApi ## CONSUMES =20 [Depex] diff --git a/IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/Ba= seFspWrapperPlatformLibSample.inf b/IntelFsp2WrapperPkg/Library/BaseFspWrap= perPlatformLibSample/BaseFspWrapperPlatformLibSample.inf index 3bc024459f..f9581e8456 100644 --- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/BaseFspWr= apperPlatformLibSample.inf +++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperPlatformLibSample/BaseFspWr= apperPlatformLibSample.inf @@ -55,3 +55,6 @@ =20 [LibraryClasses] =20 +[Pcd] + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES --=20 2.13.3.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel