From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: star.zeng@intel.com) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by groups.io with SMTP; Sun, 19 May 2019 20:32:34 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 May 2019 20:32:33 -0700 X-ExtLoop1: 1 Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga004.jf.intel.com with ESMTP; 19 May 2019 20:32:33 -0700 Received: from fmsmsx161.amr.corp.intel.com (10.18.125.9) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.408.0; Sun, 19 May 2019 20:32:33 -0700 Received: from shsmsx154.ccr.corp.intel.com (10.239.6.54) by FMSMSX161.amr.corp.intel.com (10.18.125.9) with Microsoft SMTP Server (TLS) id 14.3.408.0; Sun, 19 May 2019 20:32:32 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.249]) by SHSMSX154.ccr.corp.intel.com ([169.254.7.136]) with mapi id 14.03.0415.000; Mon, 20 May 2019 11:32:31 +0800 From: "Zeng, Star" To: "Jerry Zhou(BJ-RD)" , "edk2-devel@lists.01.org" , "devel@edk2.groups.io" CC: "Yao, Jiewen" , "Ni, Ray" , "Zeng, Star" Subject: Re: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code Thread-Topic: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code Thread-Index: AdUJNci9WEC63Y3xT7KjRAFsJUkP5QARFuIgAAC+ShABT1l1wA== Date: Mon, 20 May 2019 03:32:30 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB048310402E56C9@shsmsx102.ccr.corp.intel.com> References: <0C09AFA07DD0434D9E2A0C6AEB048310402DECF5@shsmsx102.ccr.corp.intel.com> <9b07851c347d4810a691ebaa64d1fa5e@zhaoxin.com> In-Reply-To: <9b07851c347d4810a691ebaa64d1fa5e@zhaoxin.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] 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Actua= lly, I agree with you.

Perso= nally, I think more rigorous flow could be like below.

1.       Clear B_GMCD_REG_TE, wait B_GSTS_REG_TE to be cleared.=

2.       Set B_GMCD_REG_SRTP, wait B_GSTS_REG_RTPS to be set.

3.       Zero R_RTADDR_REG.

=  

Not s= ure original code developer Jiewen=A1=AFs thought about this.

=  

=  

You m= ay submit Bugzilla at https://bugzilla.tianocore.org if you wait.

=  

=  

Thank= s,

Star<= o:p>

=  

From: = Jerry Zhou(BJ-RD) [mailto:JerryZhou@zhaoxin.com]
Sent: Monday, May 13, 2019 7:28 PM
To: Zeng, Star <star.zeng@intel.com>; edk2-devel@lists.01.org;= devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.yao@intel.com>; Ni, Ray <ray.ni@int= el.com>
Subject: =B4=F0=B8=B4: = [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code

 =

Got it! Thanks for you= r reply.

But you should still p= oll the B_GSTS_REG_TE bit, not the B_GSTS_REG_RTPS bit, in the judgement co= de of while() loop.

After & operation = between Reg32 and B_GSTS_REG_RTPS, the status of B_GSTS_REG_TE will be lost= .

 

A more tedious but mor= e reliable operation sequence is recommended in Vt-d specification 2.4 belo= w:

 

to update a bit field in this register at= offset X with value of Y, software

must follow below steps:

1. Tmp =3D Read GSTS_REG

2. Status =3D (Tmp & 96FFFFFFh) // Re= set the one-shot bits

3. Command =3D (Status | (Y << X))<= o:p>

4. Write Command to GCMD_REG

5. Wait until GSTS_REG[X] indicates comma= nd is serviced.

=B7=A2=BC= =FE=C8=CB: Zeng, Star [mailto:star.zeng@i= ntel.com]
=B7=A2=CB=CD=CA=B1=BC=E4: 2019=C4=EA5=D4=C213=C8=D5 18:54
=CA=D5=BC=FE=C8=CB: Jerry Zhou(BJ-RD); <= a href=3D"mailto:edk2-devel@lists.01.org"> edk2-devel@lists.01.org
=B3=AD=CB=CD: Yao, Jiewen; Ni, Ray; Zeng= , Star
=D6=F7=CC=E2: RE: [edk2] [PATCH] IntelSi= liconPkg VTdDxe: a question about the source code

 =

Good = question, my understanding is setting B_GMCD_REG_SRTP(BIT30) ONLY also mean= s clearing B_GMCD_REG_TE (BIT31).

=  

Thank= s,

Star<= o:p>

From: = Jerry Zhou(BJ-RD) [mailto:JerryZho= u@zhaoxin.com]
Sent: Monday, May 13, 2019 10:59 AM
To: Zeng, Star <star.zeng@= intel.com>; edk2-devel@lists.01.org
Cc: Yao, Jiewen <jiewen.y= ao@intel.com>; Ni, Ray <ray.n= i@intel.com>
Subject: =B4=F0=B8=B4: = [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code

 =

Hi Star,

         = I'am so interested in DMA protection in UEFI. It's a really good design!

         = But I have a question about the implemention of DisableDmar() in IntelSiliconPkg\feature\vtd\intelvtddxe\VtdReg.c<= /o:p>

         = Is it a typing error in the code segment below?

 

    //

    // Disable VTd

    //

    MmioWrite32 (mVtdUnitInformati= on[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);

    do {

      Reg32 =3D MmioRead= 32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GSTS_REG);

} while((Reg32 &= B_GSTS_REG_RTPS) =3D=3D 0);

 

The software should = program the B_GMCD_REG_TE field in global command register and then poll the = B_GSTS_REG_TE field in global status register if the DMAR is expected t= o be disabled or enabled according to Vt-d specification.

 

Thanks

Jerry Zhou

Ext:892418

 

 

 

-----=D3=CA=BC=FE=D4=AD=BC=FE-----
=B7=A2=BC=FE=C8=CB<= /span>: edk2-devel [mail= to:edk2-devel-bounces@lists.01.org] =B4=FA=B1=ED= Star Zeng
=B7=A2=CB=CD=CA=B1= =BC=E4: 2018= =C4=EA10=D4= =C224=C8=D5<= /span> 11:32
=CA=D5=BC=FE=C8=CB<= /span>: edk2-devel@lists.01.org
=B3=AD=CB=CD= : Jiewen Yao; Star Zeng
=D6=F7=CC=E2= : [edk2] [PATCH] IntelSiliconPkg VTdDxe: Option to force no early access at= tr request

 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1272

 

To have high confidence in usage for platform, ad= d option (BIT2 of

PcdVTdPolicyPropertyMask) to force no IOMMU acces= s attribute request

recording before DMAR table is installed.

 

Check PcdVTdPolicyPropertyMask BIT2 before Reques= tAccessAttribute()

and ProcessRequestedAccessAttribute(), then Reque= stAccessAttribute(),

ProcessRequestedAccessAttribute() and mAccessRequ= estXXX variables

could be optimized by compiler when PcdVTdPolicyP= ropertyMask BIT2 =3D 1.

 

Test done:

1: Created case that has IOMMU access attribute r= equest before DMAR

   table is installed, ASSERT was trigg= ered after setting

   PcdVTdPolicyPropertyMask BIT2 to 1.<= o:p>

 

2. Confirmed RequestAccessAttribute(), ProcessReq= uestedAccessAttribute()

   and mAccessRequestXXX variables were= optimized by compiler after

   setting PcdVTdPolicyPropertyMask BIT= 2 to 1.

 

Cc: Jiewen Yao <jiewen.yao@intel.com>

Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>

Contributed-under: TianoCore Contribution Agreeme= nt 1.1

Signed-off-by: Star Zeng <star.zeng@intel.com>

---

IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtec= tion.c | 8 +++++++-

IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdD= xe.c   | 7 +++++++

IntelSiliconPkg/IntelSiliconPkg.dec  &n= bsp;            = ;      | 1 +

3 files changed, 15 insertions(+), 1 deletion= (-)

 

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTd= Dxe/DmaProtection.c b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection= .c

index 86d50eb6f288..7784545631b3 100644

--- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Dma= Protection.c

+++ b/IntelSiliconPkg/Feature/VTd/Int= elVTdDxe/DmaProtection.c

@@ -515,7 +515,13 @@ SetupVtd (

 

   ParseDmarAcpiTableRmrr ();=

 

-  ProcessRequestedAccessAttribute ();<= /o:p>

+  if ((PcdGet8 (PcdVTdPolicyPropertyMas= k) & BIT2) =3D=3D 0) {

+    //

+    // Support IOMMU access a= ttribute request recording before DMAR table is installed.

+    // Here is to process the= requests.

+    //

+    ProcessRequestedAccessAtt= ribute ();

+  }

 

   for (Index =3D 0; Index < mV= tdUnitNumber; Index++) {

     DEBUG ((DEBUG_INFO,"= ;VTD Unit %d (Segment: %04x)\n", Index, mVtdUnitInformation[Index].Seg= ment));

diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTd= Dxe/IntelVTdDxe.c b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c

index 25d7c80af1d4..09948ce50e94 100644

--- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Int= elVTdDxe.c

+++ b/IntelSiliconPkg/Feature/VTd/Int= elVTdDxe/IntelVTdDxe.c

@@ -254,6 +254,13 @@ VTdSetAttribute (

     // Record the entry to d= river global variable.

     // As such once VTd is a= ctivated, the setting can be adopted.

     //

+    if ((PcdGet8 (PcdVTdPolic= yPropertyMask) & BIT2) !=3D 0) {

+      //=

+      // Force no I= OMMU access attribute request recording before DMAR table is installed.

+      //=

+      ASSERT_EFI_ER= ROR (EFI_NOT_READY);

+      return EFI_NO= T_READY;

+    }

     Status =3D RequestAccess= Attribute (Segment, SourceId, DeviceAddress, Length, IoMmuAccess);

   } else {

     PERF_CODE (

diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec = b/IntelSiliconPkg/IntelSiliconPkg.dec

index b9646d773b95..900e8f63c64d 100644

--- a/IntelSiliconPkg/IntelSiliconPkg.dec

+++ b/IntelSiliconPkg/IntelSiliconPkg= .dec

@@ -64,6 +64,7 @@ [PcdsFixedAtBuild, PcdsPatc= hableInModule, PcdsDynamic, PcdsDynamicEx]

   ## The mask is used to control VTd b= ehavior.<BR><BR>

   #  BIT0: Enable IOMMU during bo= ot (If DMAR table is installed in DXE. If VTD_INFO_PPI is installed in PEI.= )

   #  BIT1: Enable IOMMU when tran= sfer control to OS (ExitBootService in normal boot. EndOfPEI in S3)

+  #  BIT2: Force no IOMMU access a= ttribute request recording before DMAR table is installed.

   # @Prompt The policy for VTd driver = behavior.

   gIntelSiliconPkgTokenSpaceGuid.PcdVT= dPolicyPropertyMask|1|UINT8|0x00000002

 

--

2.7.0.windows.1

 

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