From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: star.zeng@intel.com) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by groups.io with SMTP; Sun, 07 Jul 2019 07:58:24 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Jul 2019 07:58:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,463,1557212400"; d="scan'208";a="363997744" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by fmsmga006.fm.intel.com with ESMTP; 07 Jul 2019 07:58:24 -0700 Received: from fmsmsx161.amr.corp.intel.com (10.18.125.9) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 7 Jul 2019 07:58:23 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX161.amr.corp.intel.com (10.18.125.9) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 7 Jul 2019 07:58:23 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.3]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.110]) with mapi id 14.03.0439.000; Sun, 7 Jul 2019 22:58:21 +0800 From: "Zeng, Star" To: "coeur@gmx.fr" , "devel@edk2.groups.io" , "Desimone, Nathaniel L" , "Chiu, Chasel" CC: "Zeng, Star" Subject: Re: [PATCH] IntelFsp2Pkg: Fix various typos Thread-Topic: [PATCH] IntelFsp2Pkg: Fix various typos Thread-Index: AQHVMzxmv/DpGD1YKEiRtU32sj6nUqa/Qjqw Date: Sun, 7 Jul 2019 14:58:20 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483104035BA2E@shsmsx102.ccr.corp.intel.com> References: <20190705141705.82437-1-coeur@gmx.fr> In-Reply-To: <20190705141705.82437-1-coeur@gmx.fr> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNGY4MmJjNjgtZDNmMi00YTQ2LTgwYTYtYjliZDdmNDA5MzBiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiODZZYlFjZVk0TlBHTFhLc1wvQWxqdFl4VEJmRkhvMFJJbGo2cE82NzFMM2tcL0FYeU9jcXlmV01HanFETTc0aWRlIn0= dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: star.zeng@intel.com Content-Language: en-US Content-Type: text/plain; charset="windows-1256" Content-Transfer-Encoding: quoted-printable Reviewed-by: Star Zeng > -----Original Message----- > From: Antoine C=9Cur [mailto:coeur@gmx.fr] > Sent: Friday, July 5, 2019 10:17 PM > To: devel@edk2.groups.io; Desimone, Nathaniel L > ; Zeng, Star ; Chiu, > Chasel > Cc: Antoine C=9Cur > Subject: [PATCH] IntelFsp2Pkg: Fix various typos >=20 > Fix various typos in IntelFsp2Pkg. > --- > .../FspSecCore/Ia32/FspApiEntryM.nasm | 4 +-- > .../FspSecCore/Ia32/InitializeFpu.nasm | 2 +- > .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 2 +- > IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 2 +- > IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +- > IntelFsp2Pkg/FspSecCore/SecMain.c | 2 +- > .../FspSecCore/Vtf0/Ia16/ResetVec.asm16 | 2 +- > IntelFsp2Pkg/Include/FspEas/FspApi.h | 6 ++-- > .../Include/Library/FspSecPlatformLib.h | 2 +- > IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c | 10 +++--- > .../BaseFspDebugLibSerialPort/DebugLib.c | 34 +++++++++---------- > .../BaseFspSwitchStackLib/Ia32/Stack.nasm | 2 +- > .../SecFspSecPlatformLibNull/Ia32/Flat32.nasm | 2 +- > .../PlatformSecLibNull.c | 2 +- > IntelFsp2Pkg/Tools/GenCfgOpt.py | 2 +- > IntelFsp2Pkg/Tools/PatchFv.py | 2 +- > .../Tools/UserManuals/GenCfgOptUserManual.md | 2 +- > .../Tools/UserManuals/PatchFvUserManual.md | 2 +- > 18 files changed, 41 insertions(+), 41 deletions(-) >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > index f14c18c7b9..e7261b41cd 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm > @@ -194,9 +194,9 @@ StackSetupDone: >=20 > ; > ; Pass BFV into the PEI Core > - ; It uses relative address to calucate the actual boot FV base > + ; It uses relative address to calculate the actual boot FV base > ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase > and > - ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs, > + ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs, > ; they are different. The code below can handle both cases. > ; > call ASM_PFX(AsmGetFspBaseAddress) > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > index e1886ea11b..c45520c6c1 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm > @@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits): > fldcw [ASM_PFX(mFpuControlWord)] >=20 > ; > - ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] =3D 1) to test > + ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to test > ; whether the processor supports SSE instruction. > ; > mov eax, 1 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > index b257deb76c..09cb813497 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc > @@ -150,7 +150,7 @@ NextAddress: > fldcw [FpuControlWord] >=20 > ; > - ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] =3D 1) t= o test > + ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to > + test > ; whether the processor supports SSE instruction. > ; > mov eax, 1 > diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > index d72212ed45..f183d0d10b 100644 > --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm > @@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack): > mov esp, eax ; From now, esp is pointed to per= manent > memory >=20 > ; > - ; Fixup the ebp point to permenent memory > + ; Fixup the ebp point to permanent memory > ; > mov eax, ebp > sub eax, ebx > diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c > b/IntelFsp2Pkg/FspSecCore/SecFsp.c > index 6497c88ebe..a939b7e836 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c > +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c > @@ -169,7 +169,7 @@ FspGlobalDataInit ( > SerialPortInitialize (); >=20 > // > - // Ensure the golbal data pointer is valid > + // Ensure the global data pointer is valid > // > ASSERT (GetFspGlobalDataPointer () =3D=3D PeiFspData); >=20 > diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c > b/IntelFsp2Pkg/FspSecCore/SecMain.c > index cd3ab46ce2..a63d1336e4 100644 > --- a/IntelFsp2Pkg/FspSecCore/SecMain.c > +++ b/IntelFsp2Pkg/FspSecCore/SecMain.c > @@ -110,7 +110,7 @@ SecStartup ( > // |-------------------|----> > // | | > // | | > - // | Heap | PeiTemporayRamSize > + // | Heap | PeiTemporaryRamSize > // | | > // | | > // |-------------------|----> TempRamBase diff --git > a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 > b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 > index f25de0206a..e16d692a76 100644 > --- a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 > +++ b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 > @@ -61,7 +61,7 @@ ApStartup: > ; > ; Jmp Rel16 instruction > ; Use machine code directly in case of the assembler optimization > - ; SEC entry point relatvie address will be fixed up by some build to= ol. > + ; SEC entry point relative address will be fixed up by some build to= ol. > ; > ; Typically, SEC entry point is the function _ModuleEntryPoint() def= ined in > ; SecEntry.asm > diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h > b/IntelFsp2Pkg/Include/FspEas/FspApi.h > index 1d38e639e6..dea99afc64 100644 > --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h > +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h > @@ -211,12 +211,12 @@ EFI_STATUS > each FSP release. > After FspMemInit completes its execution, it passes the pointer to the > HobList and > returns to the boot loader from where it was called. BootLoader is > responsible to > - migrate it's stack and data to Memory. > + migrate its stack and data to Memory. > FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternat= e > method to > complete the silicon initialization and provides bootloader an opportu= nity > to get > control after system memory is available and before the temporary RAM = is > torn down. >=20 > - @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data > sructure. > + @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data > structure. > @param[out] HobListPtr Pointer to receive the address of = the HOB > list. >=20 > @retval EFI_SUCCESS FSP execution environment was init= ialized > successfully. > @@ -271,7 +271,7 @@ EFI_STATUS > @retval EFI_INVALID_PARAMETER Input parameters are invalid. > @retval EFI_UNSUPPORTED The FSP calling conditions were no= t met. > @retval EFI_DEVICE_ERROR FSP initialization failed. > - @retval FSP_STATUS_RESET_REQUIREDx A reset is reuired. These status > codes will not be returned during S3. > + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status > codes will not be returned during S3. > **/ > typedef > EFI_STATUS > diff --git a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > index 48b04c5a90..bd057ecf1b 100644 > --- a/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > +++ b/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h > @@ -66,7 +66,7 @@ SecCarInit ( > ); >=20 > /** > - This function check the signture of UPD. > + This function check the signature of UPD. >=20 > @param[in] ApiIdx Internal index of the FSP API. > @param[in] ApiParam Parameter of the FSP API. > diff --git a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c > b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c > index 927cee13d3..cd404f9463 100644 > --- a/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c > +++ b/IntelFsp2Pkg/Library/BaseCacheLib/CacheLib.c > @@ -52,8 +52,8 @@ IsDefaultType ( > @param[in] BaseAddress Base address. > @param[in] Size Size. >=20 > - @retval Zero Alligned. > - @retval Non-Zero Not alligned. > + @retval Zero Aligned. > + @retval Non-Zero Not aligned. >=20 > **/ > UINT32 > @@ -217,7 +217,7 @@ Power2MaxMemory ( > } >=20 > // > - // Compute inital power of 2 size to return > + // Compute initial power of 2 size to return > // > Result =3D GetPowerOfTwo64(MemoryLength); >=20 > @@ -247,8 +247,8 @@ Power2MaxMemory ( > @param[in] BaseAddress Base address. > @param[in] Size Size. >=20 > - @retval Zero Alligned. > - @retval Non-Zero Not alligned. > + @retval Zero Aligned. > + @retval Non-Zero Not aligned. >=20 > **/ > UINT32 > diff --git a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c > b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c > index 17688c7fcb..b34905365d 100644 > --- a/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c > +++ b/IntelFsp2Pkg/Library/BaseFspDebugLibSerialPort/DebugLib.c > @@ -186,7 +186,7 @@ DebugBPrint ( > } >=20 > /** > - Convert an UINT32 value into HEX string sepcified by Buffer. > + Convert an UINT32 value into HEX string specified by Buffer. >=20 > @param Value The HEX value to convert to string > @param Buffer The pointer to the target buffer to be filled with HEX > string @@ -211,8 +211,8 @@ FillHex ( >=20 > Print a message of the form "ASSERT (): > \n" > to the debug output device. If > DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of > - PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, = if > - DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of > PcdDebugProperyMask is set then > + PcdDebugPropertyMask is set then CpuBreakpoint() is called. > + Otherwise, if DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of > + PcdDebugPropertyMask is set then > CpuDeadLoop() is called. If neither of these bits are set, then this = function > returns immediately after the message is printed to the debug output > device. > DebugAssert() must actively prevent recursion. If DebugAssert() is ca= lled > while @@ -265,8 +265,8 @@ DebugAssertInternal ( >=20 > Print a message of the form "ASSERT (): > \n" > to the debug output device. If > DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of > - PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, = if > - DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of > PcdDebugProperyMask is set then > + PcdDebugPropertyMask is set then CpuBreakpoint() is called. > + Otherwise, if DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of > + PcdDebugPropertyMask is set then > CpuDeadLoop() is called. If neither of these bits are set, then this = function > returns immediately after the message is printed to the debug output > device. > DebugAssert() must actively prevent recursion. If DebugAssert() is ca= lled > while @@ -322,10 +322,10 @@ DebugClearMemory ( > Returns TRUE if ASSERT() macros are enabled. >=20 > This function returns TRUE if the > DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of > - PcdDebugProperyMask is set. Otherwise FALSE is returned. > + PcdDebugPropertyMask is set. Otherwise FALSE is returned. >=20 > - @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of > PcdDebugProperyMask is set. > - @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of > PcdDebugProperyMask is clear. > + @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of > PcdDebugPropertyMask is set. > + @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of > PcdDebugPropertyMask is clear. >=20 > **/ > BOOLEAN > @@ -342,10 +342,10 @@ DebugAssertEnabled ( > Returns TRUE if DEBUG() macros are enabled. >=20 > This function returns TRUE if the > DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of > - PcdDebugProperyMask is set. Otherwise FALSE is returned. > + PcdDebugPropertyMask is set. Otherwise FALSE is returned. >=20 > - @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of > PcdDebugProperyMask is set. > - @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of > PcdDebugProperyMask is clear. > + @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of > PcdDebugPropertyMask is set. > + @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of > PcdDebugPropertyMask is clear. >=20 > **/ > BOOLEAN > @@ -361,10 +361,10 @@ DebugPrintEnabled ( > Returns TRUE if DEBUG_CODE() macros are enabled. >=20 > This function returns TRUE if the > DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of > - PcdDebugProperyMask is set. Otherwise FALSE is returned. > + PcdDebugPropertyMask is set. Otherwise FALSE is returned. >=20 > - @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of > PcdDebugProperyMask is set. > - @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of > PcdDebugProperyMask is clear. > + @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of > PcdDebugPropertyMask is set. > + @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of > PcdDebugPropertyMask is clear. >=20 > **/ > BOOLEAN > @@ -381,10 +381,10 @@ DebugCodeEnabled ( > Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled. >=20 > This function returns TRUE if the > DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of > - PcdDebugProperyMask is set. Otherwise FALSE is returned. > + PcdDebugPropertyMask is set. Otherwise FALSE is returned. >=20 > - @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of > PcdDebugProperyMask is set. > - @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of > PcdDebugProperyMask is clear. > + @retval TRUE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of > PcdDebugPropertyMask is set. > + @retval FALSE The DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED bit of > PcdDebugPropertyMask is clear. >=20 > **/ > BOOLEAN > diff --git a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm > b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm > index 45cc974788..aaa3fc0867 100644 > --- a/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm > +++ b/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/Ia32/Stack.nasm > @@ -5,7 +5,7 @@ > ; > ; Abstract: > ; > -; Switch the stack from temporary memory to permenent memory. > +; Switch the stack from temporary memory to permanent memory. > ; > ;-----------------------------------------------------------------------= ------- >=20 > diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.na= sm > b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm > index dc4af7c078..ff919681a8 100644 > --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm > +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/Ia32/Flat32.nasm > @@ -54,7 +54,7 @@ ASM_PFX(SecPlatformInit): > ; esp > ; > ; Description: > -; Perform any essential early platform initilaisation > +; Perform any essential early platform initialisation > ; Setup a stack > ; > ;-----------------------------------------------------------------------= ----- > diff --git > a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > index 50cb3142d2..c445190d8e 100644 > --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/PlatformSecLibNull.c > @@ -10,7 +10,7 @@ > #include >=20 > /** > - This function check the signture of UPD. > + This function check the signature of UPD. >=20 > @param[in] ApiIdx Internal index of the FSP API. > @param[in] ApiParam Parameter of the FSP API. > diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py > b/IntelFsp2Pkg/Tools/GenCfgOpt.py index c4e1e6239d..a42717caae 100644 > --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py > +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py > @@ -535,7 +535,7 @@ EndList > Offset =3D 0 > else: > if DscLine.startswith('!'): > - print("ERROR: Unrecoginized = directive for line > '%s'" % DscLine) > + print("ERROR: Unrecognized > + directive for line '%s'" % DscLine) > raise SystemExit > if not Handle: > continue > diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.p= y > index 2173984dea..edb30c816b 100644 > --- a/IntelFsp2Pkg/Tools/PatchFv.py > +++ b/IntelFsp2Pkg/Tools/PatchFv.py > @@ -160,7 +160,7 @@ class Symbols: > # > def createDicts (self, fvDir, fvNames): > # > - # If the fvDir is not a dirctory, then raise an exception > + # If the fvDir is not a directory, then raise an exception > # > if not os.path.isdir(fvDir): > raise Exception ("'%s' is not a valid directory!" % FvDir) d= iff --git > a/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md > b/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md > index 938c18416d..0a0f592801 100644 > --- a/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md > +++ b/IntelFsp2Pkg/Tools/UserManuals/GenCfgOptUserManual.md > @@ -213,7 +213,7 @@ in the third. > ```@Bsf NAME:{Variable 1} TYPE:{Combo}``` >=20 > There is a special **None** type that puts the variable in the **StructD= ef** > -region of the BSF, but doesn?t put it in any **Page** section. This make= s > the > +region of the BSF, but doesn't put it in any **Page** section. This > +makes the > variable visible to BCT, but not to the end user. >=20 > ###HELP > diff --git a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md > b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md > index becaf96b21..5f1031e729 100644 > --- a/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md > +++ b/IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md > @@ -30,7 +30,7 @@ FSP tree. >=20 > The example used contains Windows batch script %VARIABLES%. >=20 > -#FvFileBaseNames (Argument 2: 0ptional Part 1) > +#FvFileBaseNames (Argument 2: Optional Part 1) > The firmware volume file base names (**_FvFileBaseNames_**) are the > independent Fv?s that are to be patched within the FD. (0 or more in the > form > **FVFILEBASENAME:**) The colon **:** is used for delimiting the single > -- > 2.20.1 (Apple Git-117)