From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: star.zeng@intel.com) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by groups.io with SMTP; Tue, 16 Jul 2019 01:00:21 -0700 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jul 2019 01:00:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,497,1557212400"; d="scan'208,223";a="194807387" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga002.fm.intel.com with ESMTP; 16 Jul 2019 01:00:20 -0700 Received: from fmsmsx155.amr.corp.intel.com (10.18.116.71) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 16 Jul 2019 01:00:20 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX155.amr.corp.intel.com (10.18.116.71) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 16 Jul 2019 01:00:19 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.3]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.110]) with mapi id 14.03.0439.000; Tue, 16 Jul 2019 16:00:18 +0800 From: "Zeng, Star" To: "Dong, Eric" , "devel@edk2.groups.io" CC: Laszlo Ersek , "Ni, Ray" , "Kumar, Chandana C" , "Li, Kevin Y" , "Zeng, Star" Subject: Re: [PATCH] UefiCpuPkg CpuCommonFeaturesLib: Enhance Ppin code Thread-Topic: [PATCH] UefiCpuPkg CpuCommonFeaturesLib: Enhance Ppin code Thread-Index: AQHVOJplTVAJlxhy0EqQoo1+OujGbqbMV44AgACP7lA= Date: Tue, 16 Jul 2019 08:00:17 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB0483104036673A@shsmsx102.ccr.corp.intel.com> References: <20190712101258.17512-1-star.zeng@intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: star.zeng@intel.com X-Groupsio-MsgNum: 43769 Content-Language: en-US Content-Type: multipart/mixed; boundary="_002_0C09AFA07DD0434D9E2A0C6AEB0483104036673Ashsmsx102ccrcor_" --_002_0C09AFA07DD0434D9E2A0C6AEB0483104036673Ashsmsx102ccrcor_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Eric, Thanks for the comments. Attach the updated patch, and you may help push it if it is ok. Thanks, Star > -----Original Message----- > From: Dong, Eric > Sent: Tuesday, July 16, 2019 3:24 PM > To: Zeng, Star ; devel@edk2.groups.io > Cc: Laszlo Ersek ; Ni, Ray ; Kumar, > Chandana C ; Li, Kevin Y > > Subject: RE: [PATCH] UefiCpuPkg CpuCommonFeaturesLib: Enhance Ppin > code >=20 > Hi Star, >=20 > Suggest to add some code comments for the behavior, detail see the inline > comments. > with these comments, Reviewed-by: Eric Dong >=20 > Thanks, > Eric > > -----Original Message----- > > From: Zeng, Star > > Sent: Friday, July 12, 2019 6:13 PM > > To: devel@edk2.groups.io > > Cc: Zeng, Star ; Laszlo Ersek > > ; Dong, Eric ; Ni, Ray > > ; Kumar, Chandana C ; > > Li, Kevin Y > > Subject: [PATCH] UefiCpuPkg CpuCommonFeaturesLib: Enhance Ppin code > > > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1961 > > Enhance Ppin code to enable and unlock for TRUE State, and disable and > > lock for FALSE State. > > Note: enable and lock could not be set both. > > > > Cc: Laszlo Ersek > > Cc: Eric Dong > > Cc: Ray Ni > > Cc: Chandana Kumar > > Cc: Kevin Li > > Signed-off-by: Star Zeng > > --- > > .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 +++++ > > .../CpuCommonFeaturesLib.c | 2 +- > > .../Library/CpuCommonFeaturesLib/Ppin.c | 65 +++++++++++++++---- > > 3 files changed, 70 insertions(+), 12 deletions(-) > > > > diff --git > > a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h > > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h > > index 9e784e916a85..8406c6c1619f 100644 > > --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h > > +++ > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h > > @@ -863,6 +863,21 @@ FeatureControlGetConfigData ( > > IN UINTN NumberOfProcessors > > ); > > > > +/** > > + Prepares for the data used by CPU feature detection and initializati= on. > > + > > + @param[in] NumberOfProcessors The number of CPUs in the platform. > > + > > + @return Pointer to a buffer of CPU related configuration data. > > + > > + @note This service could be called by BSP only. > > +**/ > > +VOID * > > +EFIAPI > > +PpinGetConfigData ( > > + IN UINTN NumberOfProcessors > > + ); > > + > > /** > > Detects if Protected Processor Inventory Number feature supported > > on current > > processor. > > diff --git > > a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c > > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c > > index 7cc692efb649..fd43b8d66290 100644 > > --- > > a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c > > +++ > > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c > > @@ -203,7 +203,7 @@ CpuCommonFeaturesLibConstructor ( > > if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) { > > Status =3D RegisterCpuFeature ( > > "PPIN", > > - NULL, > > + PpinGetConfigData, > > PpinSupport, > > PpinInitialize, > > CPU_FEATURE_PPIN, > > diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c > > b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c > > index e8a4de8dcf60..8067cf44d015 100644 > > --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c > > +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c > > @@ -8,6 +8,28 @@ > > > > #include "CpuCommonFeatures.h" > > > > +/** > > + Prepares for the data used by CPU feature detection and initializati= on. > > + > > + @param[in] NumberOfProcessors The number of CPUs in the platform. > > + > > + @return Pointer to a buffer of CPU related configuration data. > > + > > + @note This service could be called by BSP only. > > +**/ > > +VOID * > > +EFIAPI > > +PpinGetConfigData ( > > + IN UINTN NumberOfProcessors > > + ) > > +{ > > + VOID *ConfigData; > > + > > + ConfigData =3D AllocateZeroPool (sizeof > > +(MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors); > > + ASSERT (ConfigData !=3D NULL); > > + return ConfigData; > > +} > > + > > /** > > Detects if Protected Processor Inventory Number feature supported > > on current > > processor. > > @@ -34,6 +56,7 @@ PpinSupport ( > > ) > > { > > MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER PlatformInfo; > > + MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl; > > > > if ((CpuInfo->DisplayFamily =3D=3D 0x06) && > > ((CpuInfo->DisplayModel =3D=3D 0x3E) || // Xeon E5 V2 > > @@ -47,7 +70,12 @@ PpinSupport ( > > // Check whether platform support this feature. > > // > > PlatformInfo.Uint64 =3D AsmReadMsr64 > > (MSR_IVY_BRIDGE_PLATFORM_INFO_1); > > - return (PlatformInfo.Bits.PPIN_CAP !=3D 0); > > + if (PlatformInfo.Bits.PPIN_CAP !=3D 0) { > > + MsrPpinCtrl =3D (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData; > > + ASSERT (MsrPpinCtrl !=3D NULL); > > + MsrPpinCtrl[ProcessorNumber].Uint64 =3D AsmReadMsr64 > > (MSR_IVY_BRIDGE_PPIN_CTL); > > + return TRUE; > > + } > > } > > > > return FALSE; > > @@ -73,6 +101,7 @@ PpinSupport ( > > @retval RETURN_DEVICE_ERROR Device can't change state because it > > has been > > locked. > > > > + @note This service could be called by BSP only. > > **/ > > RETURN_STATUS > > EFIAPI > > @@ -83,16 +112,18 @@ PpinInitialize ( > > IN BOOLEAN State > > ) > > { > > - MSR_IVY_BRIDGE_PPIN_CTL_REGISTER MsrPpinCtrl; > > + MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *MsrPpinCtrl; > > + > > + MsrPpinCtrl =3D (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData; > > + ASSERT (MsrPpinCtrl !=3D NULL); > > > > // > > - // Check whether device already lock this register. > > - // If already locked, just base on the request state and > > + // Check whether processor already lock this register. > > + // If already locked, just based on the request state and > > // the current state to return the status. > > // > > - MsrPpinCtrl.Uint64 =3D AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL); > > - if (MsrPpinCtrl.Bits.LockOut !=3D 0) { > > - return MsrPpinCtrl.Bits.Enable_PPIN =3D=3D State ? RETURN_SUCCESS = : > > RETURN_DEVICE_ERROR; > > + if (MsrPpinCtrl[ProcessorNumber].Bits.LockOut !=3D 0) { > > + return MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN =3D=3D State = ? > > + RETURN_SUCCESS : RETURN_DEVICE_ERROR; > > } > > > > // > > @@ -106,13 +137,25 @@ PpinInitialize ( > > return RETURN_SUCCESS; > > } > > > > - CPU_REGISTER_TABLE_WRITE_FIELD ( > > + if (State) { > > + // > > + // Enable and Unlock. > > + // > > + MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN =3D 1; > > + MsrPpinCtrl[ProcessorNumber].Bits.LockOut =3D 0; } else { >=20 > 1. I suggest to add some comments about why unlock & enable need to set > at the same time. >=20 >=20 > > + // > > + // Disable and Lock. > > + // > > + MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN =3D 0; > > + MsrPpinCtrl[ProcessorNumber].Bits.LockOut =3D 1; } >=20 >=20 > 2. Same as comments 1. >=20 > Thanks, > Eric > > + > > + CPU_REGISTER_TABLE_WRITE64 ( > > ProcessorNumber, > > Msr, > > MSR_IVY_BRIDGE_PPIN_CTL, > > - MSR_IVY_BRIDGE_PPIN_CTL_REGISTER, > > - Bits.Enable_PPIN, > > - (State) ? 1 : 0 > > + MsrPpinCtrl[ProcessorNumber].Uint64 > > ); > > > > return RETURN_SUCCESS; > > -- > > 2.21.0.windows.1 --_002_0C09AFA07DD0434D9E2A0C6AEB0483104036673Ashsmsx102ccrcor_ Content-Type: application/octet-stream; name="0001-UefiCpuPkg-CpuCommonFeaturesLib-Enhance-Ppin-code.patch" Content-Description: 0001-UefiCpuPkg-CpuCommonFeaturesLib-Enhance-Ppin-code.patch Content-Disposition: attachment; filename="0001-UefiCpuPkg-CpuCommonFeaturesLib-Enhance-Ppin-code.patch"; size=6623; creation-date="Fri, 12 Jul 2019 10:11:51 GMT"; modification-date="Tue, 16 Jul 2019 07:57:47 GMT" Content-Transfer-Encoding: base64 RnJvbSBjMThhNjY2YmNlOTk5ZWZlZGMzYmUwZDBlNDJlOTk4MGUzNmVjYjBmIE1vbiBTZXAgMTcg MDA6MDA6MDAgMjAwMQpGcm9tOiBTdGFyIFplbmcgPHN0YXIuemVuZ0BpbnRlbC5jb20+CkRhdGU6 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