From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.11207.1577266523578182680 for ; Wed, 25 Dec 2019 01:35:23 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: star.zeng@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Dec 2019 01:35:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,354,1571727600"; d="scan'208";a="219994102" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 25 Dec 2019 01:35:22 -0800 Received: from fmsmsx605.amr.corp.intel.com (10.18.126.85) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Wed, 25 Dec 2019 01:35:21 -0800 Received: from fmsmsx605.amr.corp.intel.com (10.18.126.85) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Wed, 25 Dec 2019 01:35:21 -0800 Received: from shsmsx107.ccr.corp.intel.com (10.239.4.96) by fmsmsx605.amr.corp.intel.com (10.18.126.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.1713.5 via Frontend Transport; Wed, 25 Dec 2019 01:35:21 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.109]) by SHSMSX107.ccr.corp.intel.com ([169.254.9.164]) with mapi id 14.03.0439.000; Wed, 25 Dec 2019 17:35:19 +0800 From: "Zeng, Star" To: Ray Ni , "devel@edk2.groups.io" CC: "Ni, Ray" , "Dong, Eric" , "Zeng, Star" Subject: Re: [PATCH v2 1/3] UefiCpuPkg/RegisterCpuFeaturesLib: Delete CPU_FEATURE_[BEFORE|AFTER] Thread-Topic: [PATCH v2 1/3] UefiCpuPkg/RegisterCpuFeaturesLib: Delete CPU_FEATURE_[BEFORE|AFTER] Thread-Index: AQHVpCEnQIE9yv2Nhk+VUc+H6dh5Q6fKxOYw Date: Wed, 25 Dec 2019 09:35:18 +0000 Message-ID: <0C09AFA07DD0434D9E2A0C6AEB04831040496054@shsmsx102.ccr.corp.intel.com> References: <20191126061550.494828-1-niruiyu@users.noreply.github.com> <20191126061550.494828-2-niruiyu@users.noreply.github.com> In-Reply-To: <20191126061550.494828-2-niruiyu@users.noreply.github.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: star.zeng@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Star Zeng -----Original Message----- From: Ray Ni [mailto:niruiyu@users.noreply.github.com]=20 Sent: Tuesday, November 26, 2019 2:16 PM To: devel@edk2.groups.io Cc: Ni, Ray ; Dong, Eric ; Zeng, Sta= r Subject: [PATCH v2 1/3] UefiCpuPkg/RegisterCpuFeaturesLib: Delete CPU_FEATU= RE_[BEFORE|AFTER] From: Ray Ni REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1366 Commit b3c71b472dff2c02f0cc38d7a1959cfb2ba8420d supported MSR setting in di= fferent scopes. It added below macro: CPU_FEATURE_THREAD_BEFORE CPU_FEATURE_THREAD_AFTER CPU_FEATURE_CORE_BEFORE CPU_FEATURE_CORE_AFTER CPU_FEATURE_PACKAGE_BEFORE CPU_FEATURE_PACKAGE_AFTER And it re-interpreted CPU_FEATURE_BEFORE as CPU_FEATURE_THREAD_BEFORE and C= PU_FEATURE_AFTER as CPU_FEATURE_THREAD_AFTER. This patch retires CPU_FEATURE_BEFORE and CPU_FEATURE_AFTER completely. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Star Zeng --- UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 13 ++----------- .../CpuCommonFeaturesLib/CpuCommonFeaturesLib.c | 6 +++--- .../RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 10 +++++----- 3 files changed, 10 insertions(+), 19 deletions(-) diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuP= kg/Include/Library/RegisterCpuFeaturesLib.h index f370373d63..d075606cdb 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -69,17 +69,8 @@ =20 #define CPU_FEATURE_BEFORE_ALL BIT23 #define CPU_FEATURE_AFTER_ALL BIT24 -// -// CPU_FEATURE_BEFORE and CPU_FEATURE_AFTER only mean Thread scope -// bef= ore and Thread scope after. -// It will be replace with CPU_FEATURE_THREAD_BEFORE and -// CPU_FEATURE_T= HREAD_AFTER, and should not be used anymore. -// -#define CPU_FEATURE_BEFORE BIT25 -#define CPU_FEATURE_AFTER BIT26 - -#define CPU_FEATURE_THREAD_BEFORE CPU_FEATURE_BEFORE -#define CPU_FEATURE_THREAD_AFTER CPU_FEATURE_AFTER +#define CPU_FEATURE_THREAD_BEFORE BIT25 +#define CPU_FEATURE_THREAD_AFTER BIT26 #define CPU_FEATURE_CORE_BEFORE BIT27 #define CPU_FEATURE_CORE_AFTER BIT28 #define CPU_FEATURE_PACKAGE_BEFORE BIT29 diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c= b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index 3ebd9392a9..d1fe14f519 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -95,7 +95,7 @@ CpuCommonFeaturesLibConstructor ( SmxSupport, SmxInitialize, CPU_FEATURE_SMX, - CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_BEF= ORE, + CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER |=20 + CPU_FEATURE_THREAD_BEFORE, CPU_FEATURE_END ); ASSERT_EFI_ERROR (Status); @@ -107,7 +107,7 @@ CpuCommonFeaturesLibConstructor ( VmxSupport, VmxInitialize, CPU_FEATURE_VMX, - CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_BEF= ORE, + CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER |=20 + CPU_FEATURE_THREAD_BEFORE, CPU_FEATURE_END ); ASSERT_EFI_ERROR (Status); @@ -207,7 +207,7 @@ CpuCommonFeaturesLibConstructor ( LmceSupport, LmceInitialize, CPU_FEATURE_LMCE, - CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_BEF= ORE, + CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER |=20 + CPU_FEATURE_THREAD_BEFORE, CPU_FEATURE_END ); ASSERT_EFI_ERROR (Status); diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesL= ib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c index 58910b8891..1f953832b9 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c @@ -858,16 +858,16 @@ RegisterCpuFeature ( !=3D (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER= )); ASSERT ((Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_A= FTER)) !=3D (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE= _AFTER)); - if (Feature < CPU_FEATURE_BEFORE) { + if (Feature < CPU_FEATURE_THREAD_BEFORE) { BeforeAll =3D ((Feature & CPU_FEATURE_BEFORE_ALL) !=3D 0) ? TRUE : F= ALSE; AfterAll =3D ((Feature & CPU_FEATURE_AFTER_ALL) !=3D 0) ? TRUE : FA= LSE; Feature &=3D ~(CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL); ASSERT (FeatureMask =3D=3D NULL); SetCpuFeaturesBitMask (&FeatureMask, Feature, CpuFeaturesData->BitMa= skSize); - } else if ((Feature & CPU_FEATURE_BEFORE) !=3D 0) { - SetCpuFeaturesBitMask (&BeforeFeatureBitMask, Feature & ~CPU_FEATURE= _BEFORE, CpuFeaturesData->BitMaskSize); - } else if ((Feature & CPU_FEATURE_AFTER) !=3D 0) { - SetCpuFeaturesBitMask (&AfterFeatureBitMask, Feature & ~CPU_FEATURE_= AFTER, CpuFeaturesData->BitMaskSize); + } else if ((Feature & CPU_FEATURE_THREAD_BEFORE) !=3D 0) { + SetCpuFeaturesBitMask (&BeforeFeatureBitMask, Feature & ~CPU_FEATURE= _THREAD_BEFORE, CpuFeaturesData->BitMaskSize); + } else if ((Feature & CPU_FEATURE_THREAD_AFTER) !=3D 0) { + SetCpuFeaturesBitMask (&AfterFeatureBitMask, Feature &=20 + ~CPU_FEATURE_THREAD_AFTER, CpuFeaturesData->BitMaskSize); } else if ((Feature & CPU_FEATURE_CORE_BEFORE) !=3D 0) { SetCpuFeaturesBitMask (&CoreBeforeFeatureBitMask, Feature & ~CPU_FEA= TURE_CORE_BEFORE, CpuFeaturesData->BitMaskSize); } else if ((Feature & CPU_FEATURE_CORE_AFTER) !=3D 0) { -- 2.21.0.windows.1