From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web12.7127.1663226448157708722 for ; Thu, 15 Sep 2022 00:21:25 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from lichao-PC (unknown [10.40.24.149]) by localhost.localdomain (Coremail) with SMTP id AQAAf8CxYOJJ0iJjtOMZAA--.35386S2; Thu, 15 Sep 2022 15:20:41 +0800 (CST) Date: Thu, 15 Sep 2022 15:20:36 +0800 From: "Chao Li" To: "=?utf-8?Q?devel=40edk2.groups.io?=" , "=?utf-8?Q?gaoliming=40byosoft.com.cn?=" Cc: "=?utf-8?Q?devel=40edk2.groups.io?=" , =?utf-8?Q?=22'Bob_Feng'=22?= , =?utf-8?Q?=22'Yuwei_Chen'=22?= , =?utf-8?Q?=22'Dongyan_Qian'=22?= , =?utf-8?Q?=22'Baoqi_Zhang'=22?= , =?utf-8?Q?=22'Yang_Zhou'=22?= , =?utf-8?Q?=22'Xiaotian_Wu'=22?= Message-ID: <0D46CCBC-7622-41EE-BF31-1F98BD22151B@getmailspring.com> In-Reply-To: <003901d8c8cc$3d40cc50$b7c264f0$@byosoft.com.cn> References: <003901d8c8cc$3d40cc50$b7c264f0$@byosoft.com.cn> Subject: =?UTF-8?B?UmU6IFtlZGsyLWRldmVsXSDlm57lpI06IFBBVENIIHYyIDE1LzM0XSBCYXNlVG9vbHM6IEJhc2VUb29scyBjaGFuZ2VzIGZvciBMb29uZ0FyY2ggcGxhdGZvcm0u?= X-Mailer: Mailspring MIME-Version: 1.0 X-CM-TRANSID: AQAAf8CxYOJJ0iJjtOMZAA--.35386S2 X-Coremail-Antispam: 1UD129KBjvAXoWfXFy8Cry7CFyruFWxKr4DJwb_yoWrJryrAo W7ta4xCw4kGa1IyrZ7GasFgFsrCryUG3WrJw45Gwn3GF4Iq3Z8CF4DJ34UZw4rJrW0qa1D uF9FqayDZFyrKw15n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUY27k0a2IF6w4kM7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0 x2IEx4CE42xK8VAvwI8IcIk0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj4 1l84x0c7CEw4AK67xGY2AK021l84ACjcxK6xIIjxv20xvE14v26F1j6w1UM28EF7xvwVC0 I7IYx2IY6xkF7I0E14v26r4UJVWxJr1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjc xK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVAY j202j2C_Jr0_Gr1l5I8CrVACY4xI64kE6c02F40Ex7xfMc02F40Ew4AK048IF2xKxVW8JV W5JwAv7VC0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCj c4AY6r1j6r4UMx8GjcxK6IxK0xIIj40E5I8CrwCY02Avz4vE-syl4I8I3I0E4IkC6x0Yz7 v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUGVWUWwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF 1VAY17CE14v26r1q6r43MIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6x kF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x07 b5CJdUUUUU= X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQAKCGMhxFwRLgAAsm Content-Type: multipart/alternative; boundary="6322d244_38054245_10c77" --6322d244_38054245_10c77 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Liming, Ok, I will change the commit message in the V3. Thanks, Chao -------- On 9=E6=9C=88 15 2022, at 2:27 =E4=B8=8B=E5=8D=88, "gaoliming via groups.io= " wrote: > Chao: > This change is for BaseTools C tools . The commit message can be > BaseTools: Update GenFw/GenFv to support LoongArch platform. > > The code change is good to me. Reviewed-by: Liming Gao com.cn> > > Thanks > Liming > > -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- > > =E5=8F=91=E4=BB=B6=E4=BA=BA: Chao Li > > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2022=E5=B9=B49=E6=9C=8814=E6=97= =A5 17:40 > > =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io > > =E6=8A=84=E9=80=81: Bob Feng ; Liming Gao > > ; Yuwei Chen ; > > Dongyan Qian ; Baoqi Zhang > > ; Yang Zhou ; Xiaotian > > Wu > > =E4=B8=BB=E9=A2=98: [PATCH v2 15/34] BaseTools: BaseTools changes for L= oongArch > > platform. > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053 > > > > C code changes for building EDK2 LoongArch platform. > > > > For definitions of PE/COFF and LOONGARCH relocation types, see the > > "Machine Types" and "Basic Relocation Types" sections of this URL for > > LOONGARCH values: > > https://docs.microsoft.com/en-us/windows/win32/debug/pe-format > > > > Cc: Bob Feng > > Cc: Liming Gao > > Cc: Yuwei Chen > > > > Signed-off-by: Chao Li > > Co-authored-by: Dongyan Qian > > Co-authored-by: Baoqi Zhang > > Co-authored-by: Yang Zhou > > Co-authored-by: Xiaotian Wu > > --- > > BaseTools/Source/C/Common/BasePeCoff.c | 15 +- > > BaseTools/Source/C/Common/PeCoffLoaderEx.c | 79 +++++ > > BaseTools/Source/C/GenFv/GenFvInternalLib.c | 125 +++++++- > > BaseTools/Source/C/GenFw/Elf64Convert.c | 293 > > +++++++++++++++++- > > BaseTools/Source/C/GenFw/elf_common.h | 94 ++++++ > > .../C/Include/IndustryStandard/PeImage.h | 57 ++-- > > BaseTools/Source/C/Makefiles/header.makefile | 6 + > > 7 files changed, 636 insertions(+), 33 deletions(-) > > > > diff --git a/BaseTools/Source/C/Common/BasePeCoff.c > > b/BaseTools/Source/C/Common/BasePeCoff.c > > index 62fbb2985c..30400d1341 100644 > > --- a/BaseTools/Source/C/Common/BasePeCoff.c > > +++ b/BaseTools/Source/C/Common/BasePeCoff.c > > @@ -5,6 +5,7 @@ > > Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
> > > > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> > > > Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. > All > > rights reserved.
> > > > +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. = All > > rights reserved.
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > **/ > > > > @@ -68,6 +69,14 @@ PeCoffLoaderRelocateRiscVImage ( > > IN UINT64 Adjust > > > > ); > > > > > > > > +RETURN_STATUS > > > > +PeCoffLoaderRelocateLoongArch64Image ( > > > > + IN UINT16 *Reloc, > > > > + IN OUT CHAR8 *Fixup, > > > > + IN OUT CHAR8 **FixupData, > > > > + IN UINT64 Adjust > > > > + ); > > > > + > > > > STATIC > > > > RETURN_STATUS > > > > PeCoffLoaderGetPeHeader ( > > > > @@ -184,7 +193,8 @@ Returns: > > ImageContext->Machine !=3D EFI_IMAGE_MACHINE_ARMT && \ > > > > ImageContext->Machine !=3D EFI_IMAGE_MACHINE_EBC && \ > > > > ImageContext->Machine !=3D EFI_IMAGE_MACHINE_AARCH64 && \ > > > > - ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64) { > > > > + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64 && \ > > > > + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_LOONGARCH64) > > { > > > > if (ImageContext->Machine =3D=3D IMAGE_FILE_MACHINE_ARM) { > > > > // > > > > // There are two types of ARM images. Pure ARM and ARM/Thumb. > > > > @@ -815,6 +825,9 @@ Returns: > > case EFI_IMAGE_MACHINE_RISCV64: > > > > Status =3D PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, > > &FixupData, Adjust); > > > > break; > > > > + case EFI_IMAGE_MACHINE_LOONGARCH64: > > > > + Status =3D PeCoffLoaderRelocateLoongArch64Image (Reloc, Fixup, > > &FixupData, Adjust); > > > > + break; > > > > default: > > > > Status =3D RETURN_UNSUPPORTED; > > > > break; > > > > diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c > > b/BaseTools/Source/C/Common/PeCoffLoaderEx.c > > index 799f282970..2cc428d733 100644 > > --- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c > > +++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c > > @@ -4,6 +4,7 @@ IA32 and X64 Specific relocation fixups > > Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
> > > > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> > > > Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts > > reserved.
> > > > +Copyright (c) 2022, Loongson Technology Corporation Limited. All right= s > > reserved.
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > --*/ > > > > @@ -332,3 +333,81 @@ PeCoffLoaderRelocateArmImage ( > > > > > > return RETURN_SUCCESS; > > > > } > > > > + > > > > +/** > > > > + Performs a LoongArch specific relocation fixup. > > > > + > > > > + @param[in] Reloc Pointer to the relocation record. > > > > + @param[in, out] Fixup Pointer to the address to fix up. > > > > + @param[in, out] FixupData Pointer to a buffer to log the fixups. > > > > + @param[in] Adjust The offset to adjust the fixup. > > > > + > > > > + @return Status code. > > > > +**/ > > > > +RETURN_STATUS > > > > +PeCoffLoaderRelocateLoongArch64Image ( > > > > + IN UINT16 *Reloc, > > > > + IN OUT CHAR8 *Fixup, > > > > + IN OUT CHAR8 **FixupData, > > > > + IN UINT64 Adjust > > > > + ) > > > > +{ > > > > + UINT8 RelocType; > > > > + UINT64 Value; > > > > + UINT64 Tmp1; > > > > + UINT64 Tmp2; > > > > + > > > > + RelocType =3D ((*Reloc) >> 12); > > > > + Value =3D 0; > > > > + Tmp1 =3D 0; > > > > + Tmp2 =3D 0; > > > > + > > > > + switch (RelocType) { > > > > + case EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA: > > > > + // The next four instructions are used to load a 64 bit address, > > relocate all of them > > > > + Value =3D (*(UINT32 *)Fixup & 0x1ffffe0) << 7 | // lu12i.w > > 20bits from bit5 > > > > + (*((UINT32 *)Fixup + 1) & 0x3ffc00) >> 10; // ori > > 12bits from bit10 > > > > + Tmp1 =3D *((UINT32 *)Fixup + 2) & 0x1ffffe0; // lu32i.d > > 20bits from bit5 > > > > + Tmp2 =3D *((UINT32 *)Fixup + 3) & 0x3ffc00; // lu52i.d > > 12bits from bit10 > > > > + Value =3D Value | (Tmp1 << 27) | (Tmp2 << 42); > > > > + Value +=3D Adjust; > > > > + > > > > + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> > 12) > > & 0xfffff) << 5); > > > > + if (*FixupData !=3D NULL) { > > > > + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof > > (UINT32)); > > > > + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup; > > > > + *FixupData =3D *FixupData + sizeof (UINT32); > > > > + } > > > > + > > > > + Fixup +=3D sizeof (UINT32); > > > > + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x3ffc00) | ((Value & > 0xfff) > > << 10); > > > > + if (*FixupData !=3D NULL) { > > > > + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof > > (UINT32)); > > > > + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup; > > > > + *FixupData =3D *FixupData + sizeof (UINT32); > > > > + } > > > > + > > > > + Fixup +=3D sizeof (UINT32); > > > > + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> > 32) > > & 0xfffff) << 5); > > > > + if (*FixupData !=3D NULL) { > > > > + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof > > (UINT32)); > > > > + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup; > > > > + *FixupData =3D *FixupData + sizeof (UINT32); > > > > + } > > > > + > > > > + Fixup +=3D sizeof (UINT32); > > > > + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x3ffc00) | (((Value >> 52) > > & 0xfff) << 10); > > > > + if (*FixupData !=3D NULL) { > > > > + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof > > (UINT32)); > > > > + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup; > > > > + *FixupData =3D *FixupData + sizeof (UINT32); > > > > + } > > > > + > > > > + break; > > > > + default: > > > > + Error (NULL, 0, 3000, "", "PeCoffLoaderRelocateLoongArch64Image: > > Fixup[0x%x] Adjust[0x%llx] *Reloc[0x%x], type[0x%x].", *(UINT32 *)Fixup= , > > Adjust, *Reloc, RelocType); > > > > + return RETURN_UNSUPPORTED; > > > > + } > > > > + > > > > + return RETURN_SUCCESS; > > > > +} > > > > diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > > b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > > index d650a527a5..575b99b6ad 100644 > > --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c > > +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c > > @@ -5,6 +5,7 @@ Copyright (c) 2004 - 2018, Intel Corporation. All right= s > > reserved.
> > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> > > > Portions Copyright (c) 2016 HP Development Company, L.P.
> > > > Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. > All > > rights reserved.
> > > > +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. = All > > rights reserved.
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > **/ > > > > @@ -57,6 +58,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > BOOLEAN mArm =3D FALSE; > > > > BOOLEAN mRiscV =3D FALSE; > > > > +BOOLEAN mLoongArch =3D FALSE; > > > > STATIC UINT32 MaxFfsAlignment =3D 0; > > > > BOOLEAN VtfFileFlag =3D FALSE; > > > > > > > > @@ -2416,6 +2418,98 @@ Returns: > > return EFI_SUCCESS; > > > > } > > > > > > > > +EFI_STATUS > > > > +UpdateLoongArchResetVectorIfNeeded ( > > > > + IN MEMORY_FILE *FvImage, > > > > + IN FV_INFO *FvInfo > > > > + ) > > > > +/*++ > > > > + > > > > +Routine Description: > > > > + This parses the FV looking for SEC and patches that address into the > > > > + beginning of the FV header. > > > > + > > > > + For LoongArch ISA, the reset vector is at 0x1c000000. > > > > + > > > > + We relocate it to SecCoreEntry and copy the ResetVector code to the > > > > + beginning of the FV. > > > > + > > > > +Arguments: > > > > + FvImage Memory file for the FV memory image > > > > + FvInfo Information read from INF file. > > > > + > > > > +Returns: > > > > + > > > > + EFI_SUCCESS Function Completed successfully. > > > > + EFI_ABORTED Error encountered. > > > > + EFI_INVALID_PARAMETER A required parameter was NULL. > > > > + EFI_NOT_FOUND PEI Core file not found. > > > > + > > > > +--*/ > > > > +{ > > > > + EFI_STATUS Status; > > > > + EFI_FILE_SECTION_POINTER SecPe32; > > > > + BOOLEAN UpdateVectorSec =3D FALSE; > > > > + UINT16 MachineType =3D 0; > > > > + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress =3D 0; > > > > + > > > > + // > > > > + // Verify input parameters > > > > + // > > > > + if (FvImage =3D=3D NULL || FvInfo =3D=3D NULL) { > > > > + return EFI_INVALID_PARAMETER; > > > > + } > > > > + > > > > + // > > > > + // Locate an SEC Core instance and if found extract the machine type > and > > entry point address > > > > + // > > > > + Status =3D FindCorePeSection(FvImage->FileImage, FvInfo->Size, > > EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32); > > > > + if (!EFI_ERROR(Status)) { > > > > + > > > > + Status =3D GetCoreMachineType(SecPe32, &MachineType); > > > > + if (EFI_ERROR(Status)) { > > > > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine > type > > for SEC Core."); > > > > + return EFI_ABORTED; > > > > + } > > > > + > > > > + Status =3D GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, > > SecPe32, &SecCoreEntryAddress); > > > > + if (EFI_ERROR(Status)) { > > > > + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point > > address for SEC Core."); > > > > + return EFI_ABORTED; > > > > + } > > > > + > > > > + UpdateVectorSec =3D TRUE; > > > > + } > > > > + > > > > + if (!UpdateVectorSec) > > > > + return EFI_SUCCESS; > > > > + > > > > + if (MachineType =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) { > > > > + UINT32 ResetVector[1]; > > > > + > > > > + memset(ResetVector, 0, sizeof (ResetVector)); > > > > + > > > > + /* if we found an SEC core entry point then generate a branch > > instruction */ > > > > + if (UpdateVectorSec) { > > > > + VerboseMsg("UpdateLoongArchResetVectorIfNeeded updating > > LOONGARCH64 SEC vector"); > > > > + > > > > + ResetVector[0] =3D ((SecCoreEntryAddress - FvInfo->BaseAddress) & > > 0x3FFFFFF) >> 2; > > > > + ResetVector[0] =3D ((ResetVector[0] & 0x0FFFF) << 10) | > > ((ResetVector[0] >> 16) & 0x3FF); > > > > + ResetVector[0] |=3D 0x54000000; /* bl offset */ > > > > + } > > > > + > > > > + // > > > > + // Copy to the beginning of the FV > > > > + // > > > > + memcpy(FvImage->FileImage, ResetVector, sizeof (ResetVector)); > > > > + } else { > > > > + Error(NULL, 0, 3000, "Invalid", "Unknown machine type"); > > > > + return EFI_ABORTED; > > > > + } > > > > + > > > > + return EFI_SUCCESS; > > > > +} > > > > + > > > > EFI_STATUS > > > > GetPe32Info ( > > > > IN UINT8 *Pe32, > > > > @@ -2509,7 +2603,7 @@ Returns: > > // > > > > if ((*MachineType !=3D EFI_IMAGE_MACHINE_IA32) && > > (*MachineType !=3D EFI_IMAGE_MACHINE_X64) && (*MachineType !=3D > > EFI_IMAGE_MACHINE_EBC) && > > > > (*MachineType !=3D EFI_IMAGE_MACHINE_ARMT) && > > (*MachineType !=3D EFI_IMAGE_MACHINE_AARCH64) && > > > > - (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64)) { > > > > + (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64) && > > (*MachineType !=3D EFI_IMAGE_MACHINE_LOONGARCH64)) { > > > > Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the > PE32 > > file."); > > > > return EFI_UNSUPPORTED; > > > > } > > > > @@ -2953,7 +3047,7 @@ Returns: > > goto Finish; > > > > } > > > > > > > > - if (!mArm && !mRiscV) { > > > > + if (!mArm && !mRiscV && !mLoongArch) { > > > > // > > > > // Update reset vector (SALE_ENTRY for IPF) > > > > // Now for IA32 and IA64 platform, the fv which has bsf file must > > have the > > > > @@ -3004,6 +3098,19 @@ Returns: > > FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, > > FvHeader->HeaderLength / sizeof (UINT16)); > > > > } > > > > > > > > + if (mLoongArch) { > > > > + Status =3D UpdateLoongArchResetVectorIfNeeded (&FvImageMemoryFile, > > &mFvDataInfo); > > > > + if (EFI_ERROR (Status)) { > > > > + Error (NULL, 0, 3000, "Invalid", "Could not update the reset > vector."); > > > > + goto Finish; > > > > + } > > > > + // > > > > + // Update Checksum for FvHeader > > > > + // > > > > + FvHeader->Checksum =3D 0; > > > > + FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, > > FvHeader->HeaderLength / sizeof (UINT16)); > > > > + } > > > > + > > > > // > > > > // Update FV Alignment attribute to the largest alignment of all the > FFS > > files in the FV > > > > // > > > > @@ -3450,6 +3557,12 @@ Returns: > > VerboseMsg("Located ARM/AArch64 SEC/PEI core in child FV"); > > > > mArm =3D TRUE; > > > > } > > > > + > > > > + // Machine type is LOONGARCH64, set a flag so LoongArch64 reset > > vector processed. > > > > + if ((MachineType =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64)) { > > > > + VerboseMsg("Located LoongArch64 SEC core in child FV"); > > > > + mLoongArch =3D TRUE; > > > > + } > > > > } > > > > > > > > // > > > > @@ -3608,6 +3721,10 @@ Returns: > > mRiscV =3D TRUE; > > > > } > > > > > > > > + if ( (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) ) > > { > > > > + mLoongArch =3D TRUE; > > > > + } > > > > + > > > > // > > > > // Keep Image Context for PE image in FV > > > > // > > > > @@ -3885,6 +4002,10 @@ Returns: > > mArm =3D TRUE; > > > > } > > > > > > > > + if ( (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) ) > > { > > > > + mLoongArch =3D TRUE; > > > > + } > > > > + > > > > // > > > > // Keep Image Context for TE image in FV > > > > // > > > > diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c > > b/BaseTools/Source/C/GenFw/Elf64Convert.c > > index ca3c8f8bee..ede2f0ef90 100644 > > --- a/BaseTools/Source/C/GenFw/Elf64Convert.c > > +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c > > @@ -4,6 +4,7 @@ Elf64 convert solution > > Copyright (c) 2010 - 2021, Intel Corporation. All rights reserved.
> > > > Portions copyright (c) 2013-2022, ARM Ltd. All rights reserved.
> > > > Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. > All > > rights reserved.
> > > > +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. = All > > rights reserved.
> > > > > > > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > @@ -177,7 +178,7 @@ InitializeElf64 ( > > Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or > > ET_DYN"); > > > > return FALSE; > > > > } > > > > - if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D > > EM_AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64))) { > > > > + if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D > > EM_AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64) || > > (mEhdr->e_machine =3D=3D EM_LOONGARCH))) { > > > > Warning (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64 > > machine."); > > > > } > > > > if (mEhdr->e_version !=3D EV_CURRENT) { > > > > @@ -799,6 +800,7 @@ ScanSections64 ( > > case EM_X86_64: > > > > case EM_AARCH64: > > > > case EM_RISCV64: > > > > + case EM_LOONGARCH: > > > > mCoffOffset +=3D sizeof (EFI_IMAGE_NT_HEADERS64); > > > > break; > > > > default: > > > > @@ -1088,6 +1090,10 @@ ScanSections64 ( > > NtHdr->Pe32Plus.FileHeader.Machine =3D > > EFI_IMAGE_MACHINE_RISCV64; > > > > NtHdr->Pe32Plus.OptionalHeader.Magic =3D > > EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC; > > > > break; > > > > + case EM_LOONGARCH: > > > > + NtHdr->Pe32Plus.FileHeader.Machine =3D > > EFI_IMAGE_MACHINE_LOONGARCH64; > > > > + NtHdr->Pe32Plus.OptionalHeader.Magic =3D > > EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC; > > > > + break; > > > > > > > > default: > > > > VerboseMsg ("%s unknown e_machine type. Assume X64", > > (UINTN)mEhdr->e_machine); > > > > @@ -1333,10 +1339,10 @@ WriteSections64 ( > > } > > > > > > > > // > > > > - // Skip error on EM_RISCV64 becasue no symble name is built > > > > - // from RISC-V toolchain. > > > > + // Skip error on EM_RISCV64 and EM_LOONGARCH because no > > symbol name is built > > > > + // from RISC-V and LoongArch toolchain. > > > > // > > > > - if (mEhdr->e_machine !=3D EM_RISCV64) { > > > > + if ((mEhdr->e_machine !=3D EM_RISCV64) && > > (mEhdr->e_machine !=3D EM_LOONGARCH)) { > > > > Error (NULL, 0, 3000, "Invalid", > > > > "%s: Bad definition for symbol '%s'@%#llx or > > unsupported symbol type. " > > > > "For example, absolute and undefined symbols are > > not supported.", > > > > @@ -1618,6 +1624,178 @@ WriteSections64 ( > > // Write section for RISC-V 64 architecture. > > > > // > > > > WriteSectionRiscV64 (Rel, Targ, SymShdr, Sym); > > > > + } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH) { > > > > + switch (ELF_R_TYPE(Rel->r_info)) { > > > > + INT64 Offset; > > > > + INT32 Lo, Hi; > > > > + > > > > + case R_LARCH_SOP_PUSH_ABSOLUTE: > > > > + // > > > > + // Absolute relocation. > > > > + // > > > > + *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + > > mCoffSectionsOffset[Sym->st_shndx]; > > > > + break; > > > > + > > > > + case R_LARCH_MARK_LA: > > > > + case R_LARCH_64: > > > > + case R_LARCH_NONE: > > > > + case R_LARCH_32: > > > > + case R_LARCH_RELATIVE: > > > > + case R_LARCH_COPY: > > > > + case R_LARCH_JUMP_SLOT: > > > > + case R_LARCH_TLS_DTPMOD32: > > > > + case R_LARCH_TLS_DTPMOD64: > > > > + case R_LARCH_TLS_DTPREL32: > > > > + case R_LARCH_TLS_DTPREL64: > > > > + case R_LARCH_TLS_TPREL32: > > > > + case R_LARCH_TLS_TPREL64: > > > > + case R_LARCH_IRELATIVE: > > > > + case R_LARCH_MARK_PCREL: > > > > + case R_LARCH_SOP_PUSH_PCREL: > > > > + case R_LARCH_SOP_PUSH_DUP: > > > > + case R_LARCH_SOP_PUSH_GPREL: > > > > + case R_LARCH_SOP_PUSH_TLS_TPREL: > > > > + case R_LARCH_SOP_PUSH_TLS_GOT: > > > > + case R_LARCH_SOP_PUSH_TLS_GD: > > > > + case R_LARCH_SOP_PUSH_PLT_PCREL: > > > > + case R_LARCH_SOP_ASSERT: > > > > + case R_LARCH_SOP_NOT: > > > > + case R_LARCH_SOP_SUB: > > > > + case R_LARCH_SOP_SL: > > > > + case R_LARCH_SOP_SR: > > > > + case R_LARCH_SOP_ADD: > > > > + case R_LARCH_SOP_AND: > > > > + case R_LARCH_SOP_IF_ELSE: > > > > + case R_LARCH_SOP_POP_32_S_10_5: > > > > + case R_LARCH_SOP_POP_32_U_10_12: > > > > + case R_LARCH_SOP_POP_32_S_10_12: > > > > + case R_LARCH_SOP_POP_32_S_10_16: > > > > + case R_LARCH_SOP_POP_32_S_10_16_S2: > > > > + case R_LARCH_SOP_POP_32_S_5_20: > > > > + case R_LARCH_SOP_POP_32_S_0_5_10_16_S2: > > > > + case R_LARCH_SOP_POP_32_S_0_10_10_16_S2: > > > > + case R_LARCH_SOP_POP_32_U: > > > > + case R_LARCH_ADD8: > > > > + case R_LARCH_ADD16: > > > > + case R_LARCH_ADD24: > > > > + case R_LARCH_ADD32: > > > > + case R_LARCH_ADD64: > > > > + case R_LARCH_SUB8: > > > > + case R_LARCH_SUB16: > > > > + case R_LARCH_SUB24: > > > > + case R_LARCH_SUB32: > > > > + case R_LARCH_SUB64: > > > > + case R_LARCH_GNU_VTINHERIT: > > > > + case R_LARCH_GNU_VTENTRY: > > > > + case R_LARCH_B16: > > > > + case R_LARCH_B21: > > > > + case R_LARCH_B26: > > > > + case R_LARCH_ABS_HI20: > > > > + case R_LARCH_ABS_LO12: > > > > + case R_LARCH_ABS64_LO20: > > > > + case R_LARCH_ABS64_HI12: > > > > + case R_LARCH_PCALA_LO12: > > > > + case R_LARCH_PCALA64_LO20: > > > > + case R_LARCH_PCALA64_HI12: > > > > + case R_LARCH_GOT_PC_LO12: > > > > + case R_LARCH_GOT64_PC_LO20: > > > > + case R_LARCH_GOT64_PC_HI12: > > > > + case R_LARCH_GOT64_HI20: > > > > + case R_LARCH_GOT64_LO12: > > > > + case R_LARCH_GOT64_LO20: > > > > + case R_LARCH_GOT64_HI12: > > > > + case R_LARCH_TLS_LE_HI20: > > > > + case R_LARCH_TLS_LE_LO12: > > > > + case R_LARCH_TLS_LE64_LO20: > > > > + case R_LARCH_TLS_LE64_HI12: > > > > + case R_LARCH_TLS_IE_PC_HI20: > > > > + case R_LARCH_TLS_IE_PC_LO12: > > > > + case R_LARCH_TLS_IE64_PC_LO20: > > > > + case R_LARCH_TLS_IE64_PC_HI12: > > > > + case R_LARCH_TLS_IE64_HI20: > > > > + case R_LARCH_TLS_IE64_LO12: > > > > + case R_LARCH_TLS_IE64_LO20: > > > > + case R_LARCH_TLS_IE64_HI12: > > > > + case R_LARCH_TLS_LD_PC_HI20: > > > > + case R_LARCH_TLS_LD64_HI20: > > > > + case R_LARCH_TLS_GD_PC_HI20: > > > > + case R_LARCH_TLS_GD64_HI20: > > > > + case R_LARCH_RELAX: > > > > + // > > > > + // These types are not used or do not require fixup. > > > > + // > > > > + break; > > > > + > > > > + case R_LARCH_GOT_PC_HI20: > > > > + Offset =3D Sym->st_value - (UINTN)(Targ - mCoffFile); > > > > + if (Offset < 0) { > > > > + Offset =3D (UINTN)(Targ - mCoffFile) - Sym->st_value; > > > > + Hi =3D (Offset / 0x1000) << 12; > > > > + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20; > > > > + if ((Lo < 0) && (Lo > -2048)) { > > > > + Hi +=3D 0x1000; > > > > + Lo =3D ~(0x1000 - Lo) + 1; > > > > + } > > > > + Hi =3D ~Hi + 1; > > > > + Lo =3D ~Lo + 1; > > > > + } else { > > > > + Hi =3D (Offset / 0x1000) << 12; > > > > + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20; > > > > + if (Lo < 0) { > > > > + Hi +=3D 0x1000; > > > > + Lo =3D ~(0x1000 - Lo) + 1; > > > > + } > > > > + } > > > > + // Re-encode the offset as an PCADD.D + ADDI.D(Convert > > LD.D) instruction > > > > + *(UINT32 *)Targ &=3D 0x1f; > > > > + *(UINT32 *)Targ |=3D 0x1c000000; > > > > + *(UINT32 *)Targ |=3D (((Hi >> 12) & 0xfffff) << 5); > > > > + *(UINT32 *)(Targ + 4) &=3D 0x3ff; > > > > + *(UINT32 *)(Targ + 4) |=3D 0x2c00000 | ((Lo & 0xfff) << 10); > > > > + break; > > > > + > > > > + // > > > > + // Attempt to convert instruction. > > > > + // > > > > + case R_LARCH_PCALA_HI20: > > > > + // Decode the PCALAU12I + ADDI.D instruction > > > > + Offset =3D ((INT32)((*(UINT32 *)Targ & 0x1ffffe0) << 7)); > > > > + Offset +=3D ((INT32)((*(UINT32 *)(Targ + 4) & 0x3ffc00) << 10) > >> > > 20); > > > > + // > > > > + // PCALA offset is relative to the previous page boundary, > > > > + // whereas PCADD offset is relative to the instruction > itself. > > > > + // So fix up the offset so it points to the page containing > > > > + // the symbol. > > > > + // > > > > + Offset -=3D (UINTN)(Targ - mCoffFile) & 0xfff; > > > > + if (Offset < 0) { > > > > + Offset =3D -Offset; > > > > + Hi =3D (Offset / 0x1000) << 12; > > > > + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20; > > > > + if ((Lo < 0) && (Lo > -2048)) { > > > > + Hi +=3D 0x1000; > > > > + Lo =3D ~(0x1000 - Lo) + 1; > > > > + } > > > > + Hi =3D ~Hi + 1; > > > > + Lo =3D ~Lo + 1; > > > > + } else { > > > > + Hi =3D (Offset / 0x1000) << 12; > > > > + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20; > > > > + if (Lo < 0) { > > > > + Hi +=3D 0x1000; > > > > + Lo =3D ~(0x1000 - Lo) + 1; > > > > + } > > > > + } > > > > + // Re-encode the offset as an PCADD.D + ADDI.D instruction > > > > + *(UINT32 *)Targ &=3D 0x1f; > > > > + *(UINT32 *)Targ |=3D 0x1c000000; > > > > + *(UINT32 *)Targ |=3D (((Hi >> 12) & 0xfffff) << 5); > > > > + *(UINT32 *)(Targ + 4) &=3D 0xffc003ff; > > > > + *(UINT32 *)(Targ + 4) |=3D (Lo & 0xfff) << 10; > > > > + break; > > > > + default: > > > > + Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s > > unsupported ELF EM_LOONGARCH relocation 0x%x.", mInImageName, > > (unsigned) ELF64_R_TYPE(Rel->r_info)); > > > > + } > > > > } else { > > > > Error (NULL, 0, 3000, "Invalid", "Not a supported machine > > type"); > > > > } > > > > @@ -1850,6 +2028,113 @@ WriteRelocations64 ( > > default: > > > > Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s > > unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) > > ELF_R_TYPE(Rel->r_info)); > > > > } > > > > + } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH) { > > > > + switch (ELF_R_TYPE(Rel->r_info)) { > > > > + case R_LARCH_MARK_LA: > > > > + CoffAddFixup( > > > > + (UINT32) ((UINT64) > > mCoffSectionsOffset[RelShdr->sh_info] > > > > + + (Rel->r_offset - SecShdr->sh_addr)), > > > > + EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA); > > > > + break; > > > > + case R_LARCH_64: > > > > + CoffAddFixup( > > > > + (UINT32) ((UINT64) > > mCoffSectionsOffset[RelShdr->sh_info] > > > > + + (Rel->r_offset - SecShdr->sh_addr)), > > > > + EFI_IMAGE_REL_BASED_DIR64); > > > > + break; > > > > + case R_LARCH_NONE: > > > > + case R_LARCH_32: > > > > + case R_LARCH_RELATIVE: > > > > + case R_LARCH_COPY: > > > > + case R_LARCH_JUMP_SLOT: > > > > + case R_LARCH_TLS_DTPMOD32: > > > > + case R_LARCH_TLS_DTPMOD64: > > > > + case R_LARCH_TLS_DTPREL32: > > > > + case R_LARCH_TLS_DTPREL64: > > > > + case R_LARCH_TLS_TPREL32: > > > > + case R_LARCH_TLS_TPREL64: > > > > + case R_LARCH_IRELATIVE: > > > > + case R_LARCH_MARK_PCREL: > > > > + case R_LARCH_SOP_PUSH_PCREL: > > > > + case R_LARCH_SOP_PUSH_ABSOLUTE: > > > > + case R_LARCH_SOP_PUSH_DUP: > > > > + case R_LARCH_SOP_PUSH_GPREL: > > > > + case R_LARCH_SOP_PUSH_TLS_TPREL: > > > > + case R_LARCH_SOP_PUSH_TLS_GOT: > > > > + case R_LARCH_SOP_PUSH_TLS_GD: > > > > + case R_LARCH_SOP_PUSH_PLT_PCREL: > > > > + case R_LARCH_SOP_ASSERT: > > > > + case R_LARCH_SOP_NOT: > > > > + case R_LARCH_SOP_SUB: > > > > + case R_LARCH_SOP_SL: > > > > + case R_LARCH_SOP_SR: > > > > + case R_LARCH_SOP_ADD: > > > > + case R_LARCH_SOP_AND: > > > > + case R_LARCH_SOP_IF_ELSE: > > > > + case R_LARCH_SOP_POP_32_S_10_5: > > > > + case R_LARCH_SOP_POP_32_U_10_12: > > > > + case R_LARCH_SOP_POP_32_S_10_12: > > > > + case R_LARCH_SOP_POP_32_S_10_16: > > > > + case R_LARCH_SOP_POP_32_S_10_16_S2: > > > > + case R_LARCH_SOP_POP_32_S_5_20: > > > > + case R_LARCH_SOP_POP_32_S_0_5_10_16_S2: > > > > + case R_LARCH_SOP_POP_32_S_0_10_10_16_S2: > > > > + case R_LARCH_SOP_POP_32_U: > > > > + case R_LARCH_ADD8: > > > > + case R_LARCH_ADD16: > > > > + case R_LARCH_ADD24: > > > > + case R_LARCH_ADD32: > > > > + case R_LARCH_ADD64: > > > > + case R_LARCH_SUB8: > > > > + case R_LARCH_SUB16: > > > > + case R_LARCH_SUB24: > > > > + case R_LARCH_SUB32: > > > > + case R_LARCH_SUB64: > > > > + case R_LARCH_GNU_VTINHERIT: > > > > + case R_LARCH_GNU_VTENTRY: > > > > + case R_LARCH_B16: > > > > + case R_LARCH_B21: > > > > + case R_LARCH_B26: > > > > + case R_LARCH_ABS_HI20: > > > > + case R_LARCH_ABS_LO12: > > > > + case R_LARCH_ABS64_LO20: > > > > + case R_LARCH_ABS64_HI12: > > > > + case R_LARCH_PCALA_HI20: > > > > + case R_LARCH_PCALA_LO12: > > > > + case R_LARCH_PCALA64_LO20: > > > > + case R_LARCH_PCALA64_HI12: > > > > + case R_LARCH_GOT_PC_HI20: > > > > + case R_LARCH_GOT_PC_LO12: > > > > + case R_LARCH_GOT64_PC_LO20: > > > > + case R_LARCH_GOT64_PC_HI12: > > > > + case R_LARCH_GOT64_HI20: > > > > + case R_LARCH_GOT64_LO12: > > > > + case R_LARCH_GOT64_LO20: > > > > + case R_LARCH_GOT64_HI12: > > > > + case R_LARCH_TLS_LE_HI20: > > > > + case R_LARCH_TLS_LE_LO12: > > > > + case R_LARCH_TLS_LE64_LO20: > > > > + case R_LARCH_TLS_LE64_HI12: > > > > + case R_LARCH_TLS_IE_PC_HI20: > > > > + case R_LARCH_TLS_IE_PC_LO12: > > > > + case R_LARCH_TLS_IE64_PC_LO20: > > > > + case R_LARCH_TLS_IE64_PC_HI12: > > > > + case R_LARCH_TLS_IE64_HI20: > > > > + case R_LARCH_TLS_IE64_LO12: > > > > + case R_LARCH_TLS_IE64_LO20: > > > > + case R_LARCH_TLS_IE64_HI12: > > > > + case R_LARCH_TLS_LD_PC_HI20: > > > > + case R_LARCH_TLS_LD64_HI20: > > > > + case R_LARCH_TLS_GD_PC_HI20: > > > > + case R_LARCH_TLS_GD64_HI20: > > > > + case R_LARCH_RELAX: > > > > + // > > > > + // These types are not used or do not require fixup in PE > > format files. > > > > + // > > > > + break; > > > > + default: > > > > + Error (NULL, 0, 3000, "Invalid", > > "WriteRelocations64(): %s unsupported ELF EM_LOONGARCH relocation > > 0x%x.", mInImageName, (unsigned) ELF64_R_TYPE(Rel->r_info)); > > > > + } > > > > } else { > > > > Error (NULL, 0, 3000, "Not Supported", "This tool does not > > support relocations for ELF with e_machine %u (processor type).", > (unsigned) > > mEhdr->e_machine); > > > > } > > > > diff --git a/BaseTools/Source/C/GenFw/elf_common.h > > b/BaseTools/Source/C/GenFw/elf_common.h > > index b67f59e7a0..7b7fdeb329 100644 > > --- a/BaseTools/Source/C/GenFw/elf_common.h > > +++ b/BaseTools/Source/C/GenFw/elf_common.h > > @@ -4,6 +4,7 @@ Ported ELF include files from FreeBSD > > Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
> > > > Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> > > > Portion Copyright (c) 2020, Hewlett Packard Enterprise Development LP. > All > > rights reserved.
> > > > +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. = All > > rights reserved.
> > > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > > > > > @@ -181,6 +182,7 @@ typedef struct { > > #define EM_AARCH64 183 /* ARM 64bit Architecture */ > > > > #define EM_RISCV64 243 /* 64bit RISC-V Architecture */ > > > > #define EM_RISCV 244 /* 32bit RISC-V Architecture */ > > > > +#define EM_LOONGARCH 258 /* LoongArch Architecture */ > > > > > > > > /* Non-standard or deprecated. */ > > > > #define EM_486 6 /* Intel i486. */ > > > > @@ -1042,4 +1044,96 @@ typedef struct { > > #define R_RISCV_SET8 54 > > > > #define R_RISCV_SET16 55 > > > > #define R_RISCV_SET32 56 > > > > + > > > > +/* > > > > + * LoongArch relocation types > > > > + */ > > > > +#define R_LARCH_NONE 0 > > > > +#define R_LARCH_32 1 > > > > +#define R_LARCH_64 2 > > > > +#define R_LARCH_RELATIVE 3 > > > > +#define R_LARCH_COPY 4 > > > > +#define R_LARCH_JUMP_SLOT 5 > > > > +#define R_LARCH_TLS_DTPMOD32 6 > > > > +#define R_LARCH_TLS_DTPMOD64 7 > > > > +#define R_LARCH_TLS_DTPREL32 8 > > > > +#define R_LARCH_TLS_DTPREL64 9 > > > > +#define R_LARCH_TLS_TPREL32 10 > > > > +#define R_LARCH_TLS_TPREL64 11 > > > > +#define R_LARCH_IRELATIVE 12 > > > > +#define R_LARCH_MARK_LA 20 > > > > +#define R_LARCH_MARK_PCREL 21 > > > > +#define R_LARCH_SOP_PUSH_PCREL 22 > > > > +#define R_LARCH_SOP_PUSH_ABSOLUTE 23 > > > > +#define R_LARCH_SOP_PUSH_DUP 24 > > > > +#define R_LARCH_SOP_PUSH_GPREL 25 > > > > +#define R_LARCH_SOP_PUSH_TLS_TPREL 26 > > > > +#define R_LARCH_SOP_PUSH_TLS_GOT 27 > > > > +#define R_LARCH_SOP_PUSH_TLS_GD 28 > > > > +#define R_LARCH_SOP_PUSH_PLT_PCREL 29 > > > > +#define R_LARCH_SOP_ASSERT 30 > > > > +#define R_LARCH_SOP_NOT 31 > > > > +#define R_LARCH_SOP_SUB 32 > > > > +#define R_LARCH_SOP_SL 33 > > > > +#define R_LARCH_SOP_SR 34 > > > > +#define R_LARCH_SOP_ADD 35 > > > > +#define R_LARCH_SOP_AND 36 > > > > +#define R_LARCH_SOP_IF_ELSE 37 > > > > +#define R_LARCH_SOP_POP_32_S_10_5 38 > > > > +#define R_LARCH_SOP_POP_32_U_10_12 39 > > > > +#define R_LARCH_SOP_POP_32_S_10_12 40 > > > > +#define R_LARCH_SOP_POP_32_S_10_16 41 > > > > +#define R_LARCH_SOP_POP_32_S_10_16_S2 42 > > > > +#define R_LARCH_SOP_POP_32_S_5_20 43 > > > > +#define R_LARCH_SOP_POP_32_S_0_5_10_16_S2 44 > > > > +#define R_LARCH_SOP_POP_32_S_0_10_10_16_S2 45 > > > > +#define R_LARCH_SOP_POP_32_U 46 > > > > +#define R_LARCH_ADD8 47 > > > > +#define R_LARCH_ADD16 48 > > > > +#define R_LARCH_ADD24 49 > > > > +#define R_LARCH_ADD32 50 > > > > +#define R_LARCH_ADD64 51 > > > > +#define R_LARCH_SUB8 52 > > > > +#define R_LARCH_SUB16 53 > > > > +#define R_LARCH_SUB24 54 > > > > +#define R_LARCH_SUB32 55 > > > > +#define R_LARCH_SUB64 56 > > > > +#define R_LARCH_GNU_VTINHERIT 57 > > > > +#define R_LARCH_GNU_VTENTRY 58 > > > > +#define R_LARCH_B16 64 > > > > +#define R_LARCH_B21 65 > > > > +#define R_LARCH_B26 66 > > > > +#define R_LARCH_ABS_HI20 67 > > > > +#define R_LARCH_ABS_LO12 68 > > > > +#define R_LARCH_ABS64_LO20 69 > > > > +#define R_LARCH_ABS64_HI12 70 > > > > +#define R_LARCH_PCALA_HI20 71 > > > > +#define R_LARCH_PCALA_LO12 72 > > > > +#define R_LARCH_PCALA64_LO20 73 > > > > +#define R_LARCH_PCALA64_HI12 74 > > > > +#define R_LARCH_GOT_PC_HI20 75 > > > > +#define R_LARCH_GOT_PC_LO12 76 > > > > +#define R_LARCH_GOT64_PC_LO20 77 > > > > +#define R_LARCH_GOT64_PC_HI12 78 > > > > +#define R_LARCH_GOT64_HI20 79 > > > > +#define R_LARCH_GOT64_LO12 80 > > > > +#define R_LARCH_GOT64_LO20 81 > > > > +#define R_LARCH_GOT64_HI12 82 > > > > +#define R_LARCH_TLS_LE_HI20 83 > > > > +#define R_LARCH_TLS_LE_LO12 84 > > > > +#define R_LARCH_TLS_LE64_LO20 85 > > > > +#define R_LARCH_TLS_LE64_HI12 86 > > > > +#define R_LARCH_TLS_IE_PC_HI20 87 > > > > +#define R_LARCH_TLS_IE_PC_LO12 88 > > > > +#define R_LARCH_TLS_IE64_PC_LO20 89 > > > > +#define R_LARCH_TLS_IE64_PC_HI12 90 > > > > +#define R_LARCH_TLS_IE64_HI20 91 > > > > +#define R_LARCH_TLS_IE64_LO12 92 > > > > +#define R_LARCH_TLS_IE64_LO20 93 > > > > +#define R_LARCH_TLS_IE64_HI12 94 > > > > +#define R_LARCH_TLS_LD_PC_HI20 95 > > > > +#define R_LARCH_TLS_LD64_HI20 96 > > > > +#define R_LARCH_TLS_GD_PC_HI20 97 > > > > +#define R_LARCH_TLS_GD64_HI20 98 > > > > +#define R_LARCH_RELAX 99 > > > > #endif /* !_SYS_ELF_COMMON_H_ */ > > > > diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h > > b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h > > index 21c968e650..77ded3f611 100644 > > --- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h > > +++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h > > @@ -7,6 +7,7 @@ > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> > > > Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
> > > > Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All > rights > > reserved.
> > > > + Copyright (c) 2022, Loongson Technology Corporation Limited. All righ= ts > > reserved.
> > > > > > > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > > > > > > @@ -36,23 +37,25 @@ > > // > > > > // PE32+ Machine type for EFI images > > > > // > > > > -#define IMAGE_FILE_MACHINE_I386 0x014c > > > > -#define IMAGE_FILE_MACHINE_EBC 0x0EBC > > > > -#define IMAGE_FILE_MACHINE_X64 0x8664 > > > > -#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only > > > > -#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM > > and Thumb/Thumb 2 Little Endian > > > > -#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM > > Architecture, Little Endian > > > > -#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA > > > > +#define IMAGE_FILE_MACHINE_I386 0x014c > > > > +#define IMAGE_FILE_MACHINE_EBC 0x0EBC > > > > +#define IMAGE_FILE_MACHINE_X64 0x8664 > > > > +#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only > > > > +#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed > > ARM and Thumb/Thumb 2 Little Endian > > > > +#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM > > Architecture, Little Endian > > > > +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA > > > > +#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264 // 64bit > > LoongArch Architecture > > > > > > > > // > > > > // Support old names for backward compatible > > > > // > > > > -#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386 > > > > -#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC > > > > -#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64 > > > > -#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT > > > > -#define EFI_IMAGE_MACHINE_AARCH64 > > IMAGE_FILE_MACHINE_ARM64 > > > > -#define EFI_IMAGE_MACHINE_RISCV64 > > IMAGE_FILE_MACHINE_RISCV64 > > > > +#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386 > > > > +#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC > > > > +#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64 > > > > +#define EFI_IMAGE_MACHINE_ARMT > > IMAGE_FILE_MACHINE_ARMT > > > > +#define EFI_IMAGE_MACHINE_AARCH64 > > IMAGE_FILE_MACHINE_ARM64 > > > > +#define EFI_IMAGE_MACHINE_RISCV64 > > IMAGE_FILE_MACHINE_RISCV64 > > > > +#define EFI_IMAGE_MACHINE_LOONGARCH64 > > IMAGE_FILE_MACHINE_LOONGARCH64 > > > > > > > > #define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ > > > > #define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE > > > > @@ -500,19 +503,21 @@ typedef struct { > > // > > > > // Based relocation types. > > > > // > > > > -#define EFI_IMAGE_REL_BASED_ABSOLUTE 0 > > > > -#define EFI_IMAGE_REL_BASED_HIGH 1 > > > > -#define EFI_IMAGE_REL_BASED_LOW 2 > > > > -#define EFI_IMAGE_REL_BASED_HIGHLOW 3 > > > > -#define EFI_IMAGE_REL_BASED_HIGHADJ 4 > > > > -#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5 > > > > -#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5 > > > > -#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 > > > > -#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7 > > > > -#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 > > > > -#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 > > > > -#define EFI_IMAGE_REL_BASED_IA64_IMM64 9 > > > > -#define EFI_IMAGE_REL_BASED_DIR64 10 > > > > +#define EFI_IMAGE_REL_BASED_ABSOLUTE 0 > > > > +#define EFI_IMAGE_REL_BASED_HIGH 1 > > > > +#define EFI_IMAGE_REL_BASED_LOW 2 > > > > +#define EFI_IMAGE_REL_BASED_HIGHLOW 3 > > > > +#define EFI_IMAGE_REL_BASED_HIGHADJ 4 > > > > +#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5 > > > > +#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5 > > > > +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5 > > > > +#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7 > > > > +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7 > > > > +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8 > > > > +#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8 > > > > +#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8 > > > > +#define EFI_IMAGE_REL_BASED_IA64_IMM64 9 > > > > +#define EFI_IMAGE_REL_BASED_DIR64 10 > > > > > > > > > > > > /// > > > > diff --git a/BaseTools/Source/C/Makefiles/header.makefile > > b/BaseTools/Source/C/Makefiles/header.makefile > > index 0df728f327..4e88a4fbd8 100644 > > --- a/BaseTools/Source/C/Makefiles/header.makefile > > +++ b/BaseTools/Source/C/Makefiles/header.makefile > > @@ -31,6 +31,9 @@ ifndef HOST_ARCH > > ifneq (,$(findstring riscv64,$(uname_m))) > > > > HOST_ARCH=3DRISCV64 > > > > endif > > > > + ifneq (,$(findstring loongarch64,$(uname_m))) > > > > + HOST_ARCH=3DLOONGARCH64 > > > > + endif > > > > ifndef HOST_ARCH > > > > $(info Could not detected HOST_ARCH from uname results) > > > > $(error HOST_ARCH is not defined!) > > > > @@ -70,6 +73,9 @@ ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/AArch64/ > > else ifeq ($(HOST_ARCH), RISCV64) > > > > ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/RiscV64/ > > > > > > > > +else ifeq ($(HOST_ARCH), LOONGARCH64) > > > > +ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/LoongArch64/ > > > > + > > > > else > > > > $(error Bad HOST_ARCH) > > > > endif > > > > -- > > 2.27.0 > > > > > > > > >=20 > --6322d244_38054245_10c77 Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline
Liming,
Ok, I will change the commit message in the V3.


Thanks,
Chao
--------

On 9=E6=9C=88 15 2022, at 2:27 =E4=B8= =8B=E5=8D=88, "gaoliming via groups.io" <gaoliming=3Dbyosoft.com.cn@grou= ps.io> wrote:
Chao:
This change is = for BaseTools C tools . The commit message can be
BaseTools: Upda= te GenFw/GenFv to support LoongArch platform.

The code change= is good to me. Reviewed-by: Liming Gao <gaoliming@byosoft.
co= m.cn>

Thanks
Liming
> -----=E9=82= =AE=E4=BB=B6=E5=8E=9F=E4=BB=B6-----
> =E5=8F=91=E4=BB=B6=E4=BA= =BA: Chao Li <lichao@loongson.cn>
> =E5=8F=91=E9=80=81= =E6=97=B6=E9=97=B4: 2022=E5=B9=B49=E6=9C=8814=E6=97=A5 17:40
>= =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io
> =E6=8A=84= =E9=80=81: Bob Feng <bob.c.feng@intel.com>; Liming Gao
>= <gaoliming@byosoft.com.cn>; Yuwei Chen <yuwei.chen@intel.com>;=
> Dongyan Qian <qiandongyan@loongson.cn>; Baoqi Zhang
> <zhangbaoqi@loongson.cn>; Yang Zhou <zhouyang@loongs= on.cn>; Xiaotian
> Wu <wuxiaotian@loongson.cn>
<= div>> =E4=B8=BB=E9=A2=98: [PATCH v2 15/34] BaseTools: BaseTools changes = for LoongArch
> platform.
>
> REF: h= ttps://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
>
> C code changes for building EDK2 LoongArch platform.
>=
> For definitions of PE/COFF and LOONGARCH relocation types, = see the
> "Machine Types" and "Basic Relocation Types" section= s of this URL for
> LOONGARCH values:
> https://d= ocs.microsoft.com/en-us/windows/win32/debug/pe-format
>
<= div>> Cc: Bob Feng <bob.c.feng@intel.com>
> Cc: Limin= g Gao <gaoliming@byosoft.com.cn>
> Cc: Yuwei Chen <yu= wei.chen@intel.com>
>
> Signed-off-by: Chao Li= <lichao@loongson.cn>
> Co-authored-by: Dongyan Qian <= ;qiandongyan@loongson.cn>
> Co-authored-by: Baoqi Zhang <= ;zhangbaoqi@loongson.cn>
> Co-authored-by: Yang Zhou <zh= ouyang@loongson.cn>
> Co-authored-by: Xiaotian Wu <wuxia= otian@loongson.cn>
> ---
> BaseTools/Source/C/= Common/BasePeCoff.c | 15 +-
> BaseTools/Source/C/Common/PeCoff= LoaderEx.c | 79 +++++
> BaseTools/Source/C/GenFv/GenFvInternal= Lib.c | 125 +++++++-
> BaseTools/Source/C/GenFw/Elf64Convert.c= | 293
> +++++++++++++++++-
> BaseTools/Source/C/= GenFw/elf_common.h | 94 ++++++
> .../C/Include/IndustryStandar= d/PeImage.h | 57 ++--
> BaseTools/Source/C/Makefiles/header.ma= kefile | 6 +
> 7 files changed, 636 insertions(+), 33 deletion= s(-)
>
> diff --git a/BaseTools/Source/C/Common/B= asePeCoff.c
> b/BaseTools/Source/C/Common/BasePeCoff.c
> index 62fbb2985c..30400d1341 100644
> --- a/BaseTools/= Source/C/Common/BasePeCoff.c
> +++ b/BaseTools/Source/C/Common= /BasePeCoff.c
> @@ -5,6 +5,7 @@
> Copyright (c) 2= 004 - 2018, Intel Corporation. All rights reserved.<BR>
>= ;
> Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights re= served.<BR>
>
> Portions Copyright (c) 2020= , Hewlett Packard Enterprise Development LP.
All
> r= ights reserved.<BR>
>
> +Portions Copyright= (c) 2022, Loongson Technology Corporation Limited. All
> righ= ts reserved.<BR>
>
> SPDX-License-Identifie= r: BSD-2-Clause-Patent
>
>
>
> **/
>
> @@ -68,6 +69,14 @@ PeCoffLoaderRe= locateRiscVImage (
> IN UINT64 Adjust
>
> );
>
>
>
> +RETUR= N_STATUS
>
> +PeCoffLoaderRelocateLoongArch64Imag= e (
>
> + IN UINT16 *Reloc,
>
<= div>> + IN OUT CHAR8 *Fixup,
>
> + IN OUT CHAR= 8 **FixupData,
>
> + IN UINT64 Adjust
&= gt;
> + );
>
> +
>
> STATIC
>
> RETURN_STATUS
>= ;
> PeCoffLoaderGetPeHeader (
>
> @@= -184,7 +193,8 @@ Returns:
> ImageContext->Machine !=3D EFI= _IMAGE_MACHINE_ARMT && \
>
> ImageContext= ->Machine !=3D EFI_IMAGE_MACHINE_EBC && \
>
> ImageContext->Machine !=3D EFI_IMAGE_MACHINE_AARCH64 && = \
>
> - ImageContext->Machine !=3D EFI_IMAGE_M= ACHINE_RISCV64) {
>
> + ImageContext->Machine = !=3D EFI_IMAGE_MACHINE_RISCV64 && \
>
> += ImageContext->Machine !=3D EFI_IMAGE_MACHINE_LOONGARCH64)
>= ; {
>
> if (ImageContext->Machine =3D=3D IMAGE= _FILE_MACHINE_ARM) {
>
> //
>
<= div>> // There are two types of ARM images. Pure ARM and ARM/Thumb.
>
> @@ -815,6 +825,9 @@ Returns:
> case = EFI_IMAGE_MACHINE_RISCV64:
>
> Status =3D PeCoffL= oaderRelocateRiscVImage (Reloc, Fixup,
> &FixupData, Adjus= t);
>
> break;
>
> + ca= se EFI_IMAGE_MACHINE_LOONGARCH64:
>
> + Status = =3D PeCoffLoaderRelocateLoongArch64Image (Reloc, Fixup,
> &= ;FixupData, Adjust);
>
> + break;
><= /div>
> default:
>
> Status =3D RETURN_UNS= UPPORTED;
>
> break;
>
>= ; diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c
> b/= BaseTools/Source/C/Common/PeCoffLoaderEx.c
> index 799f282970.= .2cc428d733 100644
> --- a/BaseTools/Source/C/Common/PeCoffLoa= derEx.c
> +++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
> @@ -4,6 +4,7 @@ IA32 and X64 Specific relocation fixups
> Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.&= lt;BR>
>
> Portions Copyright (c) 2011 - 2013,= ARM Ltd. All rights reserved.<BR>
>
> Copy= right (c) 2020, Hewlett Packard Enterprise Development LP. All rights
=
> reserved.<BR>
>
> +Copyright (c) = 2022, Loongson Technology Corporation Limited. All rights
> re= served.<BR>
>
> SPDX-License-Identifier: BS= D-2-Clause-Patent
>
>
>
&g= t; --*/
>
> @@ -332,3 +333,81 @@ PeCoffLoaderRelo= cateArmImage (
>
>
> return RETURN_S= UCCESS;
>
> }
>
> +
>
> +/**
>
> + Performs a = LoongArch specific relocation fixup.
>
> +
<= div>>
> + @param[in] Reloc Pointer to the relocation record= .
>
> + @param[in, out] Fixup Pointer to the addr= ess to fix up.
>
> + @param[in, out] FixupData Po= inter to a buffer to log the fixups.
>
> + @param= [in] Adjust The offset to adjust the fixup.
>
> +=
>
> + @return Status code.
>
<= div>> +**/
>
> +RETURN_STATUS
>
> +PeCoffLoaderRelocateLoongArch64Image (
>
<= div>> + IN UINT16 *Reloc,
>
> + IN OUT CHAR8 *= Fixup,
>
> + IN OUT CHAR8 **FixupData,
= >
> + IN UINT64 Adjust
>
> + )
>
> +{
>
> + UINT8 RelocT= ype;
>
> + UINT64 Value;
>
> + UINT64 Tmp1;
>
> + UINT64 Tmp2;
>
> +
>
> + RelocType =3D ((*Rel= oc) >> 12);
>
> + Value =3D 0;
&g= t;
> + Tmp1 =3D 0;
>
> + Tmp2 =3D 0;=
>
> +
>
> + switch (Re= locType) {
>
> + case EFI_IMAGE_REL_BASED_LOONGAR= CH64_MARK_LA:
>
> + // The next four instructions= are used to load a 64 bit address,
> relocate all of them
>
> + Value =3D (*(UINT32 *)Fixup & 0x1ffffe0) &= lt;< 7 | // lu12i.w
> 20bits from bit5
>
=
> + (*((UINT32 *)Fixup + 1) & 0x3ffc00) >> 10; // ori
> 12bits from bit10
>
> + Tmp1 =3D *((U= INT32 *)Fixup + 2) & 0x1ffffe0; // lu32i.d
> 20bits from b= it5
>
> + Tmp2 =3D *((UINT32 *)Fixup + 3) & 0= x3ffc00; // lu52i.d
> 12bits from bit10
>
> + Value =3D Value | (Tmp1 << 27) | (Tmp2 << 42);
<= div>>
> + Value +=3D Adjust;
>
> = +
>
> + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup &a= mp; ~0x1ffffe0) | (((Value >>
12)
> & 0xff= fff) << 5);
>
> + if (*FixupData !=3D NULL)= {
>
> + *FixupData =3D ALIGN_POINTER (*FixupData= , sizeof
> (UINT32));
>
> + *(UINT32= *)(*FixupData) =3D *(UINT32 *)Fixup;
>
> + *Fixu= pData =3D *FixupData + sizeof (UINT32);
>
> + }
>
> +
>
> + Fixup +=3D s= izeof (UINT32);
>
> + *(UINT32 *)Fixup =3D (*(UIN= T32 *)Fixup & ~0x3ffc00) | ((Value &
0xfff)
>= ; << 10);
>
> + if (*FixupData !=3D NULL) {=
>
> + *FixupData =3D ALIGN_POINTER (*FixupData, = sizeof
> (UINT32));
>
> + *(UINT32 *= )(*FixupData) =3D *(UINT32 *)Fixup;
>
> + *FixupD= ata =3D *FixupData + sizeof (UINT32);
>
> + }
>
> +
>
> + Fixup +=3D siz= eof (UINT32);
>
> + *(UINT32 *)Fixup =3D (*(UINT3= 2 *)Fixup & ~0x1ffffe0) | (((Value >>
32)
>= ; & 0xfffff) << 5);
>
> + if (*FixupDat= a !=3D NULL) {
>
> + *FixupData =3D ALIGN_POINTER= (*FixupData, sizeof
> (UINT32));
>
>= ; + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;
>
= > + *FixupData =3D *FixupData + sizeof (UINT32);
>
> + }
>
> +
>
> + = Fixup +=3D sizeof (UINT32);
>
> + *(UINT32 *)Fixu= p =3D (*(UINT32 *)Fixup & ~0x3ffc00) | (((Value >> 52)
= > & 0xfff) << 10);
>
> + if (*FixupD= ata !=3D NULL) {
>
> + *FixupData =3D ALIGN_POINT= ER (*FixupData, sizeof
> (UINT32));
>
&= gt; + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;
>
> + *FixupData =3D *FixupData + sizeof (UINT32);
>
<= div>> + }
>
> +
>
> = + break;
>
> + default:
>
= > + Error (NULL, 0, 3000, "", "PeCoffLoaderRelocateLoongArch64Image:
> Fixup[0x%x] Adjust[0x%llx] *Reloc[0x%x], type[0x%x].", *(UINT32= *)Fixup,
> Adjust, *Reloc, RelocType);
>
> + return RETURN_UNSUPPORTED;
>
> + }
>
> +
>
> + return RETURN_S= UCCESS;
>
> +}
>
> diff= --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
> b/BaseT= ools/Source/C/GenFv/GenFvInternalLib.c
> index d650a527a5..575= b99b6ad 100644
> --- a/BaseTools/Source/C/GenFv/GenFvInternalL= ib.c
> +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
=
> @@ -5,6 +5,7 @@ Copyright (c) 2004 - 2018, Intel Corporation. All= rights
> reserved.<BR>
> Portions Copyrigh= t (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
>
> Portions Copyright (c) 2016 HP Development Company, L.P.<B= R>
>
> Portions Copyright (c) 2020, Hewlett Pa= ckard Enterprise Development LP.
All
> rights reserv= ed.<BR>
>
> +Portions Copyright (c) 2022, L= oongson Technology Corporation Limited. All
> rights reserved.= <BR>
>
> SPDX-License-Identifier: BSD-2-Cla= use-Patent
>
>
>
> **/<= /div>
>
> @@ -57,6 +58,7 @@ SPDX-License-Identifier: BS= D-2-Clause-Patent
>
>
> BOOLEAN mArm= =3D FALSE;
>
> BOOLEAN mRiscV =3D FALSE;
>
> +BOOLEAN mLoongArch =3D FALSE;
>
<= div>> STATIC UINT32 MaxFfsAlignment =3D 0;
>
>= BOOLEAN VtfFileFlag =3D FALSE;
>
>
>= ;
> @@ -2416,6 +2418,98 @@ Returns:
> return EFI_= SUCCESS;
>
> }
>
>
>
> +EFI_STATUS
>
> +Update= LoongArchResetVectorIfNeeded (
>
> + IN MEMORY_FI= LE *FvImage,
>
> + IN FV_INFO *FvInfo
&= gt;
> + )
>
> +/*++
>
> +
>
> +Routine Description:
>
> + This parses the FV looking for SEC and patches tha= t address into the
>
> + beginning of the FV head= er.
>
> +
>
> + For Loo= ngArch ISA, the reset vector is at 0x1c000000.
>
>= ; +
>
> + We relocate it to SecCoreEntry and copy= the ResetVector code to the
>
> + beginning of t= he FV.
>
> +
>
> +Argum= ents:
>
> + FvImage Memory file for the FV memory= image
>
> + FvInfo Information read from INF fil= e.
>
> +
>
> +Returns:<= /div>
>
> +
>
> + EFI_SUCCESS= Function Completed successfully.
>
> + EFI_ABORT= ED Error encountered.
>
> + EFI_INVALID_PARAMETER= A required parameter was NULL.
>
> + EFI_NOT_FOU= ND PEI Core file not found.
>
> +
><= /div>
> +--*/
>
> +{
>
<= div>> + EFI_STATUS Status;
>
> + EFI_FILE_SECT= ION_POINTER SecPe32;
>
> + BOOLEAN UpdateVectorSe= c =3D FALSE;
>
> + UINT16 MachineType =3D 0;
>
> + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress =3D 0;=
>
> +
>
> + //
>
> + // Verify input parameters
>
> + //
>
> + if (FvImage =3D=3D NULL || FvIn= fo =3D=3D NULL) {
>
> + return EFI_INVALID_PARAME= TER;
>
> + }
>
> +
>
> + //
>
> + // Locate an= SEC Core instance and if found extract the machine type
and
> entry point address
>
> + //
>
> + Status =3D FindCorePeSection(FvImage->FileImage, = FvInfo->Size,
> EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32= );
>
> + if (!EFI_ERROR(Status)) {
>=
> +
>
> + Status =3D GetCoreMachine= Type(SecPe32, &MachineType);
>
> + if (EFI_ER= ROR(Status)) {
>
> + Error(NULL, 0, 3000, "Invali= d", "Could not get the PE32 machine
type
> for SEC C= ore.");
>
> + return EFI_ABORTED;
><= /div>
> + }
>
> +
>
> + Status =3D GetCoreEntryPointAddress(FvImage->FileImage, FvInfo,<= /div>
> SecPe32, &SecCoreEntryAddress);
>
> + if (EFI_ERROR(Status)) {
>
> + Error(NULL= , 0, 3000, "Invalid", "Could not get the PE32 entry point
> ad= dress for SEC Core.");
>
> + return EFI_ABORTED;<= /div>
>
> + }
>
> +
>
> + UpdateVectorSec =3D TRUE;
>
&= gt; + }
>
> +
>
> + if = (!UpdateVectorSec)
>
> + return EFI_SUCCESS;
>
> +
>
> + if (MachineType= =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) {
>
> + UI= NT32 ResetVector[1];
>
> +
>
> + memset(ResetVector, 0, sizeof (ResetVector));
>
> +
>
> + /* if we found an SEC core ent= ry point then generate a branch
> instruction */
>= ;
> + if (UpdateVectorSec) {
>
> + V= erboseMsg("UpdateLoongArchResetVectorIfNeeded updating
> LOONG= ARCH64 SEC vector");
>
> +
>
> + ResetVector[0] =3D ((SecCoreEntryAddress - FvInfo->BaseAddress= ) &
> 0x3FFFFFF) >> 2;
>
>= + ResetVector[0] =3D ((ResetVector[0] & 0x0FFFF) << 10) |
<= div>> ((ResetVector[0] >> 16) & 0x3FF);
>
> + ResetVector[0] |=3D 0x54000000; /* bl offset */
>
> + }
>
> +
>
&= gt; + //
>
> + // Copy to the beginning of the FV=
>
> + //
>
> + memcpy(= FvImage->FileImage, ResetVector, sizeof (ResetVector));
>
> + } else {
>
> + Error(NULL, 0, 300= 0, "Invalid", "Unknown machine type");
>
> + retu= rn EFI_ABORTED;
>
> + }
>
= > +
>
> + return EFI_SUCCESS;
>
> +}
>
> +
>
&= gt; EFI_STATUS
>
> GetPe32Info (
>
> IN UINT8 *Pe32,
>
> @@ -2509,7 +260= 3,7 @@ Returns:
> //
>
> if ((*Machi= neType !=3D EFI_IMAGE_MACHINE_IA32) &&
> (*MachineType= !=3D EFI_IMAGE_MACHINE_X64) && (*MachineType !=3D
> E= FI_IMAGE_MACHINE_EBC) &&
>
> (*MachineTyp= e !=3D EFI_IMAGE_MACHINE_ARMT) &&
> (*MachineType !=3D= EFI_IMAGE_MACHINE_AARCH64) &&
>
> - (*Ma= chineType !=3D EFI_IMAGE_MACHINE_RISCV64)) {
>
> = + (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64) &&
> (= *MachineType !=3D EFI_IMAGE_MACHINE_LOONGARCH64)) {
>
> Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the
PE32
> file.");
>
> return = EFI_UNSUPPORTED;
>
> }
>
&= gt; @@ -2953,7 +3047,7 @@ Returns:
> goto Finish;
&g= t;
> }
>
>
>
= > - if (!mArm && !mRiscV) {
>
> + if (= !mArm && !mRiscV && !mLoongArch) {
>
> //
>
> // Update reset vector (SALE_ENTRY f= or IPF)
>
> // Now for IA32 and IA64 platform, th= e fv which has bsf file must
> have the
>
> @@ -3004,6 +3098,19 @@ Returns:
> FvHeader->Checksu= m =3D CalculateChecksum16 ((UINT16 *) FvHeader,
> FvHeader->= ;HeaderLength / sizeof (UINT16));
>
> }
>
>
>
> + if (mLoongArch) {
>
> + Status =3D UpdateLoongArchResetVectorIfNeeded (= &FvImageMemoryFile,
> &mFvDataInfo);
>
> + if (EFI_ERROR (Status)) {
>
> + Er= ror (NULL, 0, 3000, "Invalid", "Could not update the reset
vector= .");
>
> + goto Finish;
>
= > + }
>
> + //
>
> += // Update Checksum for FvHeader
>
> + //
>
> + FvHeader->Checksum =3D 0;
>
<= div>> + FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHead= er,
> FvHeader->HeaderLength / sizeof (UINT16));
= >
> + }
>
> +
>
> //
>
> // Update FV Alignment attribut= e to the largest alignment of all the
FFS
> files in= the FV
>
> //
>
> @@ -= 3450,6 +3557,12 @@ Returns:
> VerboseMsg("Located ARM/AArch64 = SEC/PEI core in child FV");
>
> mArm =3D TRUE;
>
> }
>
> +
>= ;
> + // Machine type is LOONGARCH64, set a flag so LoongArch6= 4 reset
> vector processed.
>
> + if= ((MachineType =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64)) {
>
> + VerboseMsg("Located LoongArch64 SEC core in child FV");
<= div>>
> + mLoongArch =3D TRUE;
>
>= ; + }
>
> }
>
>
>
> //
>
> @@ -3608,6 +3721,10= @@ Returns:
> mRiscV =3D TRUE;
>
> = }
>
>
>
> + if ( (Image= Context.Machine =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) )
> {
>
> + mLoongArch =3D TRUE;
>
> + }
>
> +
>
> //<= /div>
>
> // Keep Image Context for PE image in FV
>
> //
>
> @@ -3885,6 +4002= ,10 @@ Returns:
> mArm =3D TRUE;
>
>= }
>
>
>
> + if ( (Imag= eContext.Machine =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) )
> {
>
> + mLoongArch =3D TRUE;
>
> + }
>
> +
>
> //=
>
> // Keep Image Context for TE image in FV
>
> //
>
> diff --git a/Ba= seTools/Source/C/GenFw/Elf64Convert.c
> b/BaseTools/Source/C/G= enFw/Elf64Convert.c
> index ca3c8f8bee..ede2f0ef90 100644
> --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> +++= b/BaseTools/Source/C/GenFw/Elf64Convert.c
> @@ -4,6 +4,7 @@ E= lf64 convert solution
> Copyright (c) 2010 - 2021, Intel Corpo= ration. All rights reserved.<BR>
>
> Portio= ns copyright (c) 2013-2022, ARM Ltd. All rights reserved.<BR>
>
> Portions Copyright (c) 2020, Hewlett Packard Enterpr= ise Development LP.
All
> rights reserved.<BR>=
>
> +Portions Copyright (c) 2022, Loongson Techn= ology Corporation Limited. All
> rights reserved.<BR>
>
>
>
> SPDX-License-Iden= tifier: BSD-2-Clause-Patent
>
>
>
> @@ -177,7 +178,7 @@ InitializeElf64 (
> Error (NU= LL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or
> ET_DY= N");
>
> return FALSE;
>
&= gt; }
>
> - if (!((mEhdr->e_machine =3D=3D EM_= X86_64) || (mEhdr->e_machine =3D=3D
> EM_AARCH64) || (mEhdr= ->e_machine =3D=3D EM_RISCV64))) {
>
> + if (!= ((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D
> EM_AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64) ||
<= div>> (mEhdr->e_machine =3D=3D EM_LOONGARCH))) {
>
=
> Warning (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf6= 4
> machine.");
>
> }
>=
> if (mEhdr->e_version !=3D EV_CURRENT) {
>
> @@ -799,6 +800,7 @@ ScanSections64 (
> case EM_X= 86_64:
>
> case EM_AARCH64:
>
<= div>> case EM_RISCV64:
>
> + case EM_LOONGARCH= :
>
> mCoffOffset +=3D sizeof (EFI_IMAGE_NT_HEADE= RS64);
>
> break;
>
> d= efault:
>
> @@ -1088,6 +1090,10 @@ ScanSections64= (
> NtHdr->Pe32Plus.FileHeader.Machine =3D
> = EFI_IMAGE_MACHINE_RISCV64;
>
> NtHdr->Pe32Plus= .OptionalHeader.Magic =3D
> EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;=
>
> break;
>
> + case = EM_LOONGARCH:
>
> + NtHdr->Pe32Plus.FileHeader= .Machine =3D
> EFI_IMAGE_MACHINE_LOONGARCH64;
>
> + NtHdr->Pe32Plus.OptionalHeader.Magic =3D
> = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
>
> + break;
>
>
>
> default:
>
> VerboseMsg ("%s unknown e_machine type. Assume X64",=
> (UINTN)mEhdr->e_machine);
>
> = @@ -1333,10 +1339,10 @@ WriteSections64 (
> }
>
>
>
> //
>
>= ; - // Skip error on EM_RISCV64 becasue no symble name is built
&= gt;
> - // from RISC-V toolchain.
>
>= ; + // Skip error on EM_RISCV64 and EM_LOONGARCH because no
> = symbol name is built
>
> + // from RISC-V and Loo= ngArch toolchain.
>
> //
>
> - if (mEhdr->e_machine !=3D EM_RISCV64) {
>
> + if ((mEhdr->e_machine !=3D EM_RISCV64) &&
>= (mEhdr->e_machine !=3D EM_LOONGARCH)) {
>
> E= rror (NULL, 0, 3000, "Invalid",
>
> "%s: Bad defi= nition for symbol '%s'@%#llx or
> unsupported symbol type. "
>
> "For example, absolute and undefined symbols a= re
> not supported.",
>
> @@ -1618,6= +1624,178 @@ WriteSections64 (
> // Write section for RISC-V = 64 architecture.
>
> //
>
= > WriteSectionRiscV64 (Rel, Targ, SymShdr, Sym);
>
> + } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH) {
&g= t;
> + switch (ELF_R_TYPE(Rel->r_info)) {
>
> + INT64 Offset;
>
> + INT32 Lo, Hi;<= /div>
>
> +
>
> + case R_LARC= H_SOP_PUSH_ABSOLUTE:
>
> + //
>
> + // Absolute relocation.
>
> + //
>
> + *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr-= >sh_addr +
> mCoffSectionsOffset[Sym->st_shndx];
>
> + break;
>
> +
&= gt;
> + case R_LARCH_MARK_LA:
>
> + = case R_LARCH_64:
>
> + case R_LARCH_NONE:
>
> + case R_LARCH_32:
>
> + c= ase R_LARCH_RELATIVE:
>
> + case R_LARCH_COPY:
>
> + case R_LARCH_JUMP_SLOT:
>
<= div>> + case R_LARCH_TLS_DTPMOD32:
>
> + case = R_LARCH_TLS_DTPMOD64:
>
> + case R_LARCH_TLS_DTPR= EL32:
>
> + case R_LARCH_TLS_DTPREL64:
= >
> + case R_LARCH_TLS_TPREL32:
>
&g= t; + case R_LARCH_TLS_TPREL64:
>
> + case R_LARCH= _IRELATIVE:
>
> + case R_LARCH_MARK_PCREL:
<= div>>
> + case R_LARCH_SOP_PUSH_PCREL:
>
=
> + case R_LARCH_SOP_PUSH_DUP:
>
> + case= R_LARCH_SOP_PUSH_GPREL:
>
> + case R_LARCH_SOP_P= USH_TLS_TPREL:
>
> + case R_LARCH_SOP_PUSH_TLS_GO= T:
>
> + case R_LARCH_SOP_PUSH_TLS_GD:
= >
> + case R_LARCH_SOP_PUSH_PLT_PCREL:
>
=
> + case R_LARCH_SOP_ASSERT:
>
> + case R= _LARCH_SOP_NOT:
>
> + case R_LARCH_SOP_SUB:
=
>
> + case R_LARCH_SOP_SL:
>
&g= t; + case R_LARCH_SOP_SR:
>
> + case R_LARCH_SOP_= ADD:
>
> + case R_LARCH_SOP_AND:
>
> + case R_LARCH_SOP_IF_ELSE:
>
> + c= ase R_LARCH_SOP_POP_32_S_10_5:
>
> + case R_LARCH= _SOP_POP_32_U_10_12:
>
> + case R_LARCH_SOP_POP_3= 2_S_10_12:
>
> + case R_LARCH_SOP_POP_32_S_10_16:=
>
> + case R_LARCH_SOP_POP_32_S_10_16_S2:
<= div>>
> + case R_LARCH_SOP_POP_32_S_5_20:
>
> + case R_LARCH_SOP_POP_32_S_0_5_10_16_S2:
>
=
> + case R_LARCH_SOP_POP_32_S_0_10_10_16_S2:
>
> + case R_LARCH_SOP_POP_32_U:
>
> + case R= _LARCH_ADD8:
>
> + case R_LARCH_ADD16:
= >
> + case R_LARCH_ADD24:
>
> + c= ase R_LARCH_ADD32:
>
> + case R_LARCH_ADD64:
>
> + case R_LARCH_SUB8:
>
>= ; + case R_LARCH_SUB16:
>
> + case R_LARCH_SUB24:=
>
> + case R_LARCH_SUB32:
>
> + case R_LARCH_SUB64:
>
> + case R_LARCH_= GNU_VTINHERIT:
>
> + case R_LARCH_GNU_VTENTRY:
>
> + case R_LARCH_B16:
>
&g= t; + case R_LARCH_B21:
>
> + case R_LARCH_B26:
>
> + case R_LARCH_ABS_HI20:
>
> + case R_LARCH_ABS_LO12:
>
> + case R_LAR= CH_ABS64_LO20:
>
> + case R_LARCH_ABS64_HI12:
>
> + case R_LARCH_PCALA_LO12:
>
<= div>> + case R_LARCH_PCALA64_LO20:
>
> + case = R_LARCH_PCALA64_HI12:
>
> + case R_LARCH_GOT_PC_L= O12:
>
> + case R_LARCH_GOT64_PC_LO20:
= >
> + case R_LARCH_GOT64_PC_HI12:
>
= > + case R_LARCH_GOT64_HI20:
>
> + case R_LARC= H_GOT64_LO12:
>
> + case R_LARCH_GOT64_LO20:
>
> + case R_LARCH_GOT64_HI12:
>
> + case R_LARCH_TLS_LE_HI20:
>
> + case R_= LARCH_TLS_LE_LO12:
>
> + case R_LARCH_TLS_LE64_LO= 20:
>
> + case R_LARCH_TLS_LE64_HI12:
&= gt;
> + case R_LARCH_TLS_IE_PC_HI20:
>
= > + case R_LARCH_TLS_IE_PC_LO12:
>
> + case R_= LARCH_TLS_IE64_PC_LO20:
>
> + case R_LARCH_TLS_IE= 64_PC_HI12:
>
> + case R_LARCH_TLS_IE64_HI20:
>
> + case R_LARCH_TLS_IE64_LO12:
>
> + case R_LARCH_TLS_IE64_LO20:
>
> + c= ase R_LARCH_TLS_IE64_HI12:
>
> + case R_LARCH_TLS= _LD_PC_HI20:
>
> + case R_LARCH_TLS_LD64_HI20:
>
> + case R_LARCH_TLS_GD_PC_HI20:
>
> + case R_LARCH_TLS_GD64_HI20:
>
> += case R_LARCH_RELAX:
>
> + //
>
> + // These types are not used or do not require fixup.
>
> + //
>
> + break;
= >
> +
>
> + case R_LARCH_GOT_PC_H= I20:
>
> + Offset =3D Sym->st_value - (UINTN)(= Targ - mCoffFile);
>
> + if (Offset < 0) {
>
> + Offset =3D (UINTN)(Targ - mCoffFile) - Sym->= ;st_value;
>
> + Hi =3D (Offset / 0x1000) <<= ; 12;
>
> + Lo =3D (INT32)((Offset & 0xfff) &= lt;< 20) >> 20;
>
> + if ((Lo < 0) &a= mp;& (Lo > -2048)) {
>
> + Hi +=3D 0x1000;=
>
> + Lo =3D ~(0x1000 - Lo) + 1;
><= /div>
> + }
>
> + Hi =3D ~Hi + 1;
>
> + Lo =3D ~Lo + 1;
>
> + } e= lse {
>
> + Hi =3D (Offset / 0x1000) << 12;=
>
> + Lo =3D (INT32)((Offset & 0xfff) <&l= t; 20) >> 20;
>
> + if (Lo < 0) {
<= div>>
> + Hi +=3D 0x1000;
>
> + L= o =3D ~(0x1000 - Lo) + 1;
>
> + }
><= /div>
> + }
>
> + // Re-encode the offset = as an PCADD.D + ADDI.D(Convert
> LD.D) instruction
&= gt;
> + *(UINT32 *)Targ &=3D 0x1f;
>
> + *(UINT32 *)Targ |=3D 0x1c000000;
>
> + *= (UINT32 *)Targ |=3D (((Hi >> 12) & 0xfffff) << 5);
>
> + *(UINT32 *)(Targ + 4) &=3D 0x3ff;
>= ;
> + *(UINT32 *)(Targ + 4) |=3D 0x2c00000 | ((Lo & 0xfff)= << 10);
>
> + break;
>
<= div>> +
>
> + //
>
>= + // Attempt to convert instruction.
>
> + //
>
> + case R_LARCH_PCALA_HI20:
>
=
> + // Decode the PCALAU12I + ADDI.D instruction
>
> + Offset =3D ((INT32)((*(UINT32 *)Targ & 0x1ffffe0) <<= ; 7));
>
> + Offset +=3D ((INT32)((*(UINT32 *)(Ta= rg + 4) & 0x3ffc00) << 10)
>>
> 20);=
>
> + //
>
> + // PCAL= A offset is relative to the previous page boundary,
>
> + // whereas PCADD offset is relative to the instruction
i= tself.
>
> + // So fix up the offset so it points= to the page containing
>
> + // the symbol.
>
> + //
>
> + Offset -=3D = (UINTN)(Targ - mCoffFile) & 0xfff;
>
> + if (= Offset < 0) {
>
> + Offset =3D -Offset;
<= div>>
> + Hi =3D (Offset / 0x1000) << 12;
&= gt;
> + Lo =3D (INT32)((Offset & 0xfff) << 20) >&= gt; 20;
>
> + if ((Lo < 0) && (Lo >= -2048)) {
>
> + Hi +=3D 0x1000;
>
> + Lo =3D ~(0x1000 - Lo) + 1;
>
> + = }
>
> + Hi =3D ~Hi + 1;
>
= > + Lo =3D ~Lo + 1;
>
> + } else {
&= gt;
> + Hi =3D (Offset / 0x1000) << 12;
>
> + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 2= 0;
>
> + if (Lo < 0) {
>
> + Hi +=3D 0x1000;
>
> + Lo =3D ~(0x1000 - = Lo) + 1;
>
> + }
>
> + = }
>
> + // Re-encode the offset as an PCADD.D + A= DDI.D instruction
>
> + *(UINT32 *)Targ &=3D = 0x1f;
>
> + *(UINT32 *)Targ |=3D 0x1c000000;
>
> + *(UINT32 *)Targ |=3D (((Hi >> 12) & 0= xfffff) << 5);
>
> + *(UINT32 *)(Targ + 4) = &=3D 0xffc003ff;
>
> + *(UINT32 *)(Targ + 4) = |=3D (Lo & 0xfff) << 10;
>
> + break;
>
> + default:
>
> + Err= or (NULL, 0, 3000, "Invalid", "WriteSections64(): %s
> unsuppo= rted ELF EM_LOONGARCH relocation 0x%x.", mInImageName,
> (unsi= gned) ELF64_R_TYPE(Rel->r_info));
>
> + }
>
> } else {
>
> Error (NUL= L, 0, 3000, "Invalid", "Not a supported machine
> type");
>
> }
>
> @@ -1850,6 +2028,= 113 @@ WriteRelocations64 (
> default:
>
> Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s
> unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned= )
> ELF_R_TYPE(Rel->r_info));
>
>= }
>
> + } else if (mEhdr->e_machine =3D=3D EM= _LOONGARCH) {
>
> + switch (ELF_R_TYPE(Rel->r_= info)) {
>
> + case R_LARCH_MARK_LA:
&g= t;
> + CoffAddFixup(
>
> + (UINT32) = ((UINT64)
> mCoffSectionsOffset[RelShdr->sh_info]
>
> + + (Rel->r_offset - SecShdr->sh_addr)),
>
> + EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA);
>
> + break;
>
> + case R_LARCH= _64:
>
> + CoffAddFixup(
>
> + (UINT32) ((UINT64)
> mCoffSectionsOffset[RelShdr->s= h_info]
>
> + + (Rel->r_offset - SecShdr->s= h_addr)),
>
> + EFI_IMAGE_REL_BASED_DIR64);
=
>
> + break;
>
> + case R_LA= RCH_NONE:
>
> + case R_LARCH_32:
>
> + case R_LARCH_RELATIVE:
>
> + case= R_LARCH_COPY:
>
> + case R_LARCH_JUMP_SLOT:
>
> + case R_LARCH_TLS_DTPMOD32:
>
=
> + case R_LARCH_TLS_DTPMOD64:
>
> + case= R_LARCH_TLS_DTPREL32:
>
> + case R_LARCH_TLS_DTP= REL64:
>
> + case R_LARCH_TLS_TPREL32:
= >
> + case R_LARCH_TLS_TPREL64:
>
&g= t; + case R_LARCH_IRELATIVE:
>
> + case R_LARCH_M= ARK_PCREL:
>
> + case R_LARCH_SOP_PUSH_PCREL:
>
> + case R_LARCH_SOP_PUSH_ABSOLUTE:
>=
> + case R_LARCH_SOP_PUSH_DUP:
>
> = + case R_LARCH_SOP_PUSH_GPREL:
>
> + case R_LARCH= _SOP_PUSH_TLS_TPREL:
>
> + case R_LARCH_SOP_PUSH_= TLS_GOT:
>
> + case R_LARCH_SOP_PUSH_TLS_GD:
>
> + case R_LARCH_SOP_PUSH_PLT_PCREL:
>=
> + case R_LARCH_SOP_ASSERT:
>
> + = case R_LARCH_SOP_NOT:
>
> + case R_LARCH_SOP_SUB:=
>
> + case R_LARCH_SOP_SL:
>
<= div>> + case R_LARCH_SOP_SR:
>
> + case R_LARC= H_SOP_ADD:
>
> + case R_LARCH_SOP_AND:
= >
> + case R_LARCH_SOP_IF_ELSE:
>
&g= t; + case R_LARCH_SOP_POP_32_S_10_5:
>
> + case R= _LARCH_SOP_POP_32_U_10_12:
>
> + case R_LARCH_SOP= _POP_32_S_10_12:
>
> + case R_LARCH_SOP_POP_32_S_= 10_16:
>
> + case R_LARCH_SOP_POP_32_S_10_16_S2:<= /div>
>
> + case R_LARCH_SOP_POP_32_S_5_20:
&= gt;
> + case R_LARCH_SOP_POP_32_S_0_5_10_16_S2:
>=
> + case R_LARCH_SOP_POP_32_S_0_10_10_16_S2:
>
> + case R_LARCH_SOP_POP_32_U:
>
> + = case R_LARCH_ADD8:
>
> + case R_LARCH_ADD16:
>
> + case R_LARCH_ADD24:
>
&g= t; + case R_LARCH_ADD32:
>
> + case R_LARCH_ADD64= :
>
> + case R_LARCH_SUB8:
>
> + case R_LARCH_SUB16:
>
> + case R_LARCH_= SUB24:
>
> + case R_LARCH_SUB32:
>
> + case R_LARCH_SUB64:
>
> + case R_= LARCH_GNU_VTINHERIT:
>
> + case R_LARCH_GNU_VTENT= RY:
>
> + case R_LARCH_B16:
>
<= div>> + case R_LARCH_B21:
>
> + case R_LARCH_B= 26:
>
> + case R_LARCH_ABS_HI20:
>
> + case R_LARCH_ABS_LO12:
>
> + case= R_LARCH_ABS64_LO20:
>
> + case R_LARCH_ABS64_HI1= 2:
>
> + case R_LARCH_PCALA_HI20:
><= /div>
> + case R_LARCH_PCALA_LO12:
>
> + c= ase R_LARCH_PCALA64_LO20:
>
> + case R_LARCH_PCAL= A64_HI12:
>
> + case R_LARCH_GOT_PC_HI20:
>
> + case R_LARCH_GOT_PC_LO12:
>
> + case R_LARCH_GOT64_PC_LO20:
>
> + case R_= LARCH_GOT64_PC_HI12:
>
> + case R_LARCH_GOT64_HI2= 0:
>
> + case R_LARCH_GOT64_LO12:
><= /div>
> + case R_LARCH_GOT64_LO20:
>
> + c= ase R_LARCH_GOT64_HI12:
>
> + case R_LARCH_TLS_LE= _HI20:
>
> + case R_LARCH_TLS_LE_LO12:
= >
> + case R_LARCH_TLS_LE64_LO20:
>
= > + case R_LARCH_TLS_LE64_HI12:
>
> + case R_L= ARCH_TLS_IE_PC_HI20:
>
> + case R_LARCH_TLS_IE_PC= _LO12:
>
> + case R_LARCH_TLS_IE64_PC_LO20:
=
>
> + case R_LARCH_TLS_IE64_PC_HI12:
>
> + case R_LARCH_TLS_IE64_HI20:
>
> + = case R_LARCH_TLS_IE64_LO12:
>
> + case R_LARCH_TL= S_IE64_LO20:
>
> + case R_LARCH_TLS_IE64_HI12:
>
> + case R_LARCH_TLS_LD_PC_HI20:
>
> + case R_LARCH_TLS_LD64_HI20:
>
> += case R_LARCH_TLS_GD_PC_HI20:
>
> + case R_LARCH_= TLS_GD64_HI20:
>
> + case R_LARCH_RELAX:
>
> + //
>
> + // These types a= re not used or do not require fixup in PE
> format files.
>
> + //
>
> + break;
=
>
> + default:
>
> + Error (= NULL, 0, 3000, "Invalid",
> "WriteRelocations64(): %s unsuppor= ted ELF EM_LOONGARCH relocation
> 0x%x.", mInImageName, (unsig= ned) ELF64_R_TYPE(Rel->r_info));
>
> + }
=
>
> } else {
>
> Error (NULL= , 0, 3000, "Not Supported", "This tool does not
> support relo= cations for ELF with e_machine %u (processor type).",
(unsigned)<= /div>
> mEhdr->e_machine);
>
> }
<= div>>
> diff --git a/BaseTools/Source/C/GenFw/elf_common.h<= /div>
> b/BaseTools/Source/C/GenFw/elf_common.h
> index= b67f59e7a0..7b7fdeb329 100644
> --- a/BaseTools/Source/C/GenF= w/elf_common.h
> +++ b/BaseTools/Source/C/GenFw/elf_common.h
> @@ -4,6 +4,7 @@ Ported ELF include files from FreeBSD
> Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>= ;
>
> Portions Copyright (c) 2011 - 2013, ARM Ltd= . All rights reserved.<BR>
>
> Portion Copy= right (c) 2020, Hewlett Packard Enterprise Development LP.
All
> rights reserved.<BR>
>
> +Port= ions Copyright (c) 2022, Loongson Technology Corporation Limited. All
=
> rights reserved.<BR>
>
> SPDX-Lic= ense-Identifier: BSD-2-Clause-Patent
>
>
>
>
>
> @@ -181,6 +182,7 @@ typ= edef struct {
> #define EM_AARCH64 183 /* ARM 64bit Architectu= re */
>
> #define EM_RISCV64 243 /* 64bit RISC-V = Architecture */
>
> #define EM_RISCV 244 /* 32bit= RISC-V Architecture */
>
> +#define EM_LOONGARCH= 258 /* LoongArch Architecture */
>
>
&= gt;
> /* Non-standard or deprecated. */
>
> #define EM_486 6 /* Intel i486. */
>
> @@= -1042,4 +1044,96 @@ typedef struct {
> #define R_RISCV_SET8 5= 4
>
> #define R_RISCV_SET16 55
>
> #define R_RISCV_SET32 56
>
> +
<= div>>
> +/*
>
> + * LoongArch rel= ocation types
>
> + */
>
&= gt; +#define R_LARCH_NONE 0
>
> +#define R_LARCH_= 32 1
>
> +#define R_LARCH_64 2
>
> +#define R_LARCH_RELATIVE 3
>
> +#def= ine R_LARCH_COPY 4
>
> +#define R_LARCH_JUMP_SLOT= 5
>
> +#define R_LARCH_TLS_DTPMOD32 6
= >
> +#define R_LARCH_TLS_DTPMOD64 7
>
> +#define R_LARCH_TLS_DTPREL32 8
>
> +#defi= ne R_LARCH_TLS_DTPREL64 9
>
> +#define R_LARCH_TL= S_TPREL32 10
>
> +#define R_LARCH_TLS_TPREL64 11<= /div>
>
> +#define R_LARCH_IRELATIVE 12
><= /div>
> +#define R_LARCH_MARK_LA 20
>
> +#= define R_LARCH_MARK_PCREL 21
>
> +#define R_LARCH= _SOP_PUSH_PCREL 22
>
> +#define R_LARCH_SOP_PUSH_= ABSOLUTE 23
>
> +#define R_LARCH_SOP_PUSH_DUP 24<= /div>
>
> +#define R_LARCH_SOP_PUSH_GPREL 25
= >
> +#define R_LARCH_SOP_PUSH_TLS_TPREL 26
>
> +#define R_LARCH_SOP_PUSH_TLS_GOT 27
>
> +#define R_LARCH_SOP_PUSH_TLS_GD 28
>
> +#d= efine R_LARCH_SOP_PUSH_PLT_PCREL 29
>
> +#define = R_LARCH_SOP_ASSERT 30
>
> +#define R_LARCH_SOP_NO= T 31
>
> +#define R_LARCH_SOP_SUB 32
&g= t;
> +#define R_LARCH_SOP_SL 33
>
> = +#define R_LARCH_SOP_SR 34
>
> +#define R_LARCH_S= OP_ADD 35
>
> +#define R_LARCH_SOP_AND 36
>
> +#define R_LARCH_SOP_IF_ELSE 37
>
=
> +#define R_LARCH_SOP_POP_32_S_10_5 38
>
&g= t; +#define R_LARCH_SOP_POP_32_U_10_12 39
>
> +#d= efine R_LARCH_SOP_POP_32_S_10_12 40
>
> +#define = R_LARCH_SOP_POP_32_S_10_16 41
>
> +#define R_LARC= H_SOP_POP_32_S_10_16_S2 42
>
> +#define R_LARCH_S= OP_POP_32_S_5_20 43
>
> +#define R_LARCH_SOP_POP_= 32_S_0_5_10_16_S2 44
>
> +#define R_LARCH_SOP_POP= _32_S_0_10_10_16_S2 45
>
> +#define R_LARCH_SOP_P= OP_32_U 46
>
> +#define R_LARCH_ADD8 47
>
> +#define R_LARCH_ADD16 48
>
>= ; +#define R_LARCH_ADD24 49
>
> +#define R_LARCH_= ADD32 50
>
> +#define R_LARCH_ADD64 51
= >
> +#define R_LARCH_SUB8 52
>
> = +#define R_LARCH_SUB16 53
>
> +#define R_LARCH_SU= B24 54
>
> +#define R_LARCH_SUB32 55
&g= t;
> +#define R_LARCH_SUB64 56
>
> += #define R_LARCH_GNU_VTINHERIT 57
>
> +#define R_L= ARCH_GNU_VTENTRY 58
>
> +#define R_LARCH_B16 64
>
> +#define R_LARCH_B21 65
>
> +#define R_LARCH_B26 66
>
> +#define R_LA= RCH_ABS_HI20 67
>
> +#define R_LARCH_ABS_LO12 68<= /div>
>
> +#define R_LARCH_ABS64_LO20 69
>=
> +#define R_LARCH_ABS64_HI12 70
>
>= ; +#define R_LARCH_PCALA_HI20 71
>
> +#define R_L= ARCH_PCALA_LO12 72
>
> +#define R_LARCH_PCALA64_L= O20 73
>
> +#define R_LARCH_PCALA64_HI12 74
=
>
> +#define R_LARCH_GOT_PC_HI20 75
>
> +#define R_LARCH_GOT_PC_LO12 76
>
> += #define R_LARCH_GOT64_PC_LO20 77
>
> +#define R_L= ARCH_GOT64_PC_HI12 78
>
> +#define R_LARCH_GOT64_= HI20 79
>
> +#define R_LARCH_GOT64_LO12 80
<= div>>
> +#define R_LARCH_GOT64_LO20 81
>
=
> +#define R_LARCH_GOT64_HI12 82
>
> +#de= fine R_LARCH_TLS_LE_HI20 83
>
> +#define R_LARCH_= TLS_LE_LO12 84
>
> +#define R_LARCH_TLS_LE64_LO20= 85
>
> +#define R_LARCH_TLS_LE64_HI12 86
>
> +#define R_LARCH_TLS_IE_PC_HI20 87
>
> +#define R_LARCH_TLS_IE_PC_LO12 88
>
&g= t; +#define R_LARCH_TLS_IE64_PC_LO20 89
>
> +#def= ine R_LARCH_TLS_IE64_PC_HI12 90
>
> +#define R_LA= RCH_TLS_IE64_HI20 91
>
> +#define R_LARCH_TLS_IE6= 4_LO12 92
>
> +#define R_LARCH_TLS_IE64_LO20 93
>
> +#define R_LARCH_TLS_IE64_HI12 94
&g= t;
> +#define R_LARCH_TLS_LD_PC_HI20 95
>
> +#define R_LARCH_TLS_LD64_HI20 96
>
> +#d= efine R_LARCH_TLS_GD_PC_HI20 97
>
> +#define R_LA= RCH_TLS_GD64_HI20 98
>
> +#define R_LARCH_RELAX 9= 9
>
> #endif /* !_SYS_ELF_COMMON_H_ */
= >
> diff --git a/BaseTools/Source/C/Include/IndustryStandar= d/PeImage.h
> b/BaseTools/Source/C/Include/IndustryStandard/Pe= Image.h
> index 21c968e650..77ded3f611 100644
> -= -- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
> += ++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
> @= @ -7,6 +7,7 @@
> Copyright (c) 2006 - 2018, Intel Corporation.= All rights reserved.<BR>
>
> Portions copy= right (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
&g= t;
> Copyright (c) 2020, Hewlett Packard Enterprise Developmen= t LP. All
rights
> reserved.<BR>
>= ;
> + Copyright (c) 2022, Loongson Technology Corporation Limi= ted. All rights
> reserved.<BR>
>
>
>
> SPDX-License-Identifier: BSD-2-Clause-P= atent
>
>
>
> @@ -36,23= +37,25 @@
> //
>
> // PE32+ Machine= type for EFI images
>
> //
>
<= div>> -#define IMAGE_FILE_MACHINE_I386 0x014c
>
&= gt; -#define IMAGE_FILE_MACHINE_EBC 0x0EBC
>
> -#= define IMAGE_FILE_MACHINE_X64 0x8664
>
> -#define= IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
>
> = -#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM
> a= nd Thumb/Thumb 2 Little Endian
>
> -#define IMAGE= _FILE_MACHINE_ARM64 0xAA64 // 64bit ARM
> Architecture, Little= Endian
>
> -#define IMAGE_FILE_MACHINE_RISCV64 0= x5064 // 64bit RISC-V ISA
>
> +#define IMAGE_FILE= _MACHINE_I386 0x014c
>
> +#define IMAGE_FILE_MACH= INE_EBC 0x0EBC
>
> +#define IMAGE_FILE_MACHINE_X6= 4 0x8664
>
> +#define IMAGE_FILE_MACHINE_ARM 0x01= c0 // Thumb only
>
> +#define IMAGE_FILE_MACHINE_= ARMT 0x01c2 // 32bit Mixed
> ARM and Thumb/Thumb 2 Little Endi= an
>
> +#define IMAGE_FILE_MACHINE_ARM64 0xAA64 /= / 64bit ARM
> Architecture, Little Endian
>
=
> +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA
>
> +#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264 = // 64bit
> LoongArch Architecture
>
>= ;
>
> //
>
> // Support= old names for backward compatible
>
> //
>
> -#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I= 386
>
> -#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE= _MACHINE_EBC
>
> -#define EFI_IMAGE_MACHINE_X64 I= MAGE_FILE_MACHINE_X64
>
> -#define EFI_IMAGE_MACH= INE_ARMT IMAGE_FILE_MACHINE_ARMT
>
> -#define EFI= _IMAGE_MACHINE_AARCH64
> IMAGE_FILE_MACHINE_ARM64
&g= t;
> -#define EFI_IMAGE_MACHINE_RISCV64
> IMAGE_F= ILE_MACHINE_RISCV64
>
> +#define EFI_IMAGE_MACHIN= E_IA32 IMAGE_FILE_MACHINE_I386
>
> +#define EFI_I= MAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC
>
> +#def= ine EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
>
&= gt; +#define EFI_IMAGE_MACHINE_ARMT
> IMAGE_FILE_MACHINE_ARMT<= /div>
>
> +#define EFI_IMAGE_MACHINE_AARCH64
= > IMAGE_FILE_MACHINE_ARM64
>
> +#define EFI_IM= AGE_MACHINE_RISCV64
> IMAGE_FILE_MACHINE_RISCV64
>= ;
> +#define EFI_IMAGE_MACHINE_LOONGARCH64
> IMAG= E_FILE_MACHINE_LOONGARCH64
>
>
>
> #define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ
>
> #define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE
>
> @@ -500,19 +503,21 @@ typedef struct {
> //
<= div>>
> // Based relocation types.
>
> //
>
> -#define EFI_IMAGE_REL_BASED_ABSOLUT= E 0
>
> -#define EFI_IMAGE_REL_BASED_HIGH 1
=
>
> -#define EFI_IMAGE_REL_BASED_LOW 2
><= /div>
> -#define EFI_IMAGE_REL_BASED_HIGHLOW 3
>
<= div>> -#define EFI_IMAGE_REL_BASED_HIGHADJ 4
>
&g= t; -#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
>
>= ; -#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
>
> -= #define EFI_IMAGE_REL_BASED_RISCV_HI20 5
>
> -#de= fine EFI_IMAGE_REL_BASED_ARM_MOV32T 7
>
> -#defin= e EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
>
> -#define= EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
>
> -#define = EFI_IMAGE_REL_BASED_IA64_IMM64 9
>
> -#define EFI= _IMAGE_REL_BASED_DIR64 10
>
> +#define EFI_IMAGE_= REL_BASED_ABSOLUTE 0
>
> +#define EFI_IMAGE_REL_B= ASED_HIGH 1
>
> +#define EFI_IMAGE_REL_BASED_LOW = 2
>
> +#define EFI_IMAGE_REL_BASED_HIGHLOW 3
>
> +#define EFI_IMAGE_REL_BASED_HIGHADJ 4
= >
> +#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
&= gt;
> +#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
>=
> +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
>
> +#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
>
=
> +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
>
<= div>> +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
>
> +#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8
>
> +#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8
= >
> +#define EFI_IMAGE_REL_BASED_IA64_IMM64 9
>= ;
> +#define EFI_IMAGE_REL_BASED_DIR64 10
>
=
>
>
>
>
> ///
>
> diff --git a/BaseTools/Source/C/Makefiles/head= er.makefile
> b/BaseTools/Source/C/Makefiles/header.makefile
> index 0df728f327..4e88a4fbd8 100644
> --- a/Base= Tools/Source/C/Makefiles/header.makefile
> +++ b/BaseTools/Sou= rce/C/Makefiles/header.makefile
> @@ -31,6 +31,9 @@ ifndef HOS= T_ARCH
> ifneq (,$(findstring riscv64,$(uname_m)))
&= gt;
> HOST_ARCH=3DRISCV64
>
> endif<= /div>
>
> + ifneq (,$(findstring loongarch64,$(uname_m)= ))
>
> + HOST_ARCH=3DLOONGARCH64
>
> + endif
>
> ifndef HOST_ARCH
<= div>>
> $(info Could not detected HOST_ARCH from uname resu= lts)
>
> $(error HOST_ARCH is not defined!)
=
>
> @@ -70,6 +73,9 @@ ARCH_INCLUDE =3D -I $(MAKEROOT)/= Include/AArch64/
> else ifeq ($(HOST_ARCH), RISCV64)
>
> ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/RiscV64/
=
>
>
>
> +else ifeq ($(HOST_A= RCH), LOONGARCH64)
>
> +ARCH_INCLUDE =3D -I $(MAK= EROOT)/Include/LoongArch64/
>
> +
><= /div>
> else
>
> $(error Bad HOST_ARCH)
>
> endif
>
> --
> 2.27.0
>






=
3D"Sent --6322d244_38054245_10c77--