From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web09.4746.1663914782913690346 for ; Thu, 22 Sep 2022 23:33:03 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from lichao-PC (unknown [10.40.24.149]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Dx_2sYUy1jzYUgAA--.54730S2; Fri, 23 Sep 2022 14:32:56 +0800 (CST) Date: Fri, 23 Sep 2022 14:32:56 +0800 From: "Chao Li" To: Michael D Kinney Cc: Liming Gao , Zhiguang Liu , "=?utf-8?Q?devel=40edk2.groups.io?=" Message-ID: <0DD2214C-8A12-4FCB-B65B-93D00E64E4C2@getmailspring.com> In-Reply-To: <20220914094105.3696657-1-lichao@loongson.cn> References: <20220914094105.3696657-1-lichao@loongson.cn> Subject: Re: [PATCH v2 22/34] MdePkg/Include: LoongArch definitions. X-Mailer: Mailspring MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Dx_2sYUy1jzYUgAA--.54730S2 X-Coremail-Antispam: 1UD129KBjvJXoW3trWrAr17tF1kuw47XFyUAwb_yoWkCw1UpF 10kFZ7Ka47KFZ3Ww1rGF1j9rn7Gws7GryUG3yDuw4vyFWqv34vgw4DKF4fGrWDZr4kK340 vwnYy3yUur1xt3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBGb7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rw A2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xII jxv20xvEc7CjxVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4 vEx4A2jsIEc7CjxVAFwI0_GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG67k0 8I80eVWUJVW8JwAqx4xG64xvF2IEw4CE5I8CrVC2j2Wl5I8CrVAKz4kIr2xC04v26r4j6r yUMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC6x0Y z7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l7480Y4vEI4kI2Ix0rVAqx4xJMxkIecxEwVCm-w CF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r10 6r1rMI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64 vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_ Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0x vEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07boQ6XUUUUU= X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQASCGMsUF0TQAAGsM Content-Type: multipart/alternative; boundary="632d5318_623fd81b_dbe1" --632d5318_623fd81b_dbe1 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Hi Mike, In the V2, I added IANA, Microsoft and UE=46I specification links in ever= y patches that uses them. Associated patches: 0008-MdePkg-Include-Add-LOONGARCH-related-definitions-.patch 0015-BaseTools-BaseTools-changes-for-LoongArch-platfor.patch 0022-MdePkg-Include-LoongArch-definitions.patch(This patch) Please check and review them again. Thanks, Chao -------- On 9=E6=9C=88 14 2022, at 5:41 =E4=B8=8B=E5=8D=88, Chao Li wrote: > RE=46: https://bugzilla.tianocore.org/show=5Fbug.cgi=3Fid=3D4053 > > Add LoongArch processor related definitions. > =46or the Http boot and PXE boot types seeing this URL section =22Proce= ssor > Architecture Type=22 for the LOONGARCH values: > https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xh= tml > > =46or definitions of PE/CO=46=46 and LOONGARCH relocation types, see th= e > =22Machine Types=22 and =22Basic Relocation Types=22 sections of this U= RL for > LOONGARCH values: > https://docs.microsoft.com/en-us/windows/win32/debug/pe-format > > =46or the register definitions of exceptions context, see the UE=46I V2= .10 > 18.2.2, 18.2.4 and 18.2.5 sections of this URL for LOONGARCH > definitions: > https://uefi.org/specs/UE=46I/2.10/18=5FProtocols=5FDebugger=5FSupport.= html > > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > > Signed-off-by: Chao Li > --- > MdePkg/Include/IndustryStandard/PeImage.h =7C 9 ++ > MdePkg/Include/Protocol/DebugSupport.h =7C 107 ++++++++++++++++++++-- > MdePkg/Include/Protocol/PxeBaseCode.h =7C 3 + > MdePkg/Include/Uefi/UefiBaseType.h =7C 14 +++ > MdePkg/Include/Uefi/UefiSpec.h =7C 16 ++-- > 5 files changed, 136 insertions(+), 13 deletions(-) > > diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include= /IndustryStandard/PeImage.h > index 3109dc20f8..dd4cc25483 100644 > --- a/MdePkg/Include/IndustryStandard/PeImage.h > +++ b/MdePkg/Include/IndustryStandard/PeImage.h > =40=40 -10,6 +10,7 =40=40 > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> > Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
= > Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Developm= ent LP. All rights reserved.
> +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. = All rights reserved.
> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > =40=40 -38,6 +39,8 =40=40 SPDX-License-Identifier: BSD-2-Clause-Patent > =23define IMAGE=5F=46ILE=5FMACHINE=5FRISCV32 0x5032 > > =23define IMAGE=5F=46ILE=5FMACHINE=5FRISCV64 0x5064 > =23define IMAGE=5F=46ILE=5FMACHINE=5FRISCV128 0x5128 > +=23define IMAGE=5F=46ILE=5FMACHINE=5FLOONGARCH32 0x6232 > +=23define IMAGE=5F=46ILE=5FMACHINE=5FLOONGARCH64 0x6264 > > > // > // EXE file formats > =40=40 -503,6 +506,12 =40=40 typedef struct =7B > =23define E=46I=5FIMAGE=5FREL=5FBASED=5FRISCV=5FLOW12I 7 > > =23define E=46I=5FIMAGE=5FREL=5FBASED=5FRISCV=5FLOW12S 8 > > > +// > +// Relocation types of LoongArch processor. > +// > +=23define E=46I=5FIMAGE=5FREL=5FBASED=5FLOONGARCH32=5FMARK=5FLA 8 > +=23define E=46I=5FIMAGE=5FREL=5FBASED=5FLOONGARCH64=5FMARK=5FLA 8 > + > /// > /// Line number format. > /// > diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Pr= otocol/DebugSupport.h > index ec5b92a5c5..2b0ae2d157 100644 > --- a/MdePkg/Include/Protocol/DebugSupport.h > +++ b/MdePkg/Include/Protocol/DebugSupport.h > =40=40 -654,17 +654,110 =40=40 typedef struct =7B > UINT64 X31; > > =7D E=46I=5FSYSTEM=5FCONTEXT=5FRISCV64; > > > +// > +// LoongArch processor exception types. > +// > +=23define EXCEPT=5FLOONGARCH=5FINT 0 > +=23define EXCEPT=5FLOONGARCH=5FPIL 1 > +=23define EXCEPT=5FLOONGARCH=5FPIS 2 > +=23define EXCEPT=5FLOONGARCH=5FPI=46 3 > +=23define EXCEPT=5FLOONGARCH=5FPME 4 > +=23define EXCEPT=5FLOONGARCH=5FPNR 5 > +=23define EXCEPT=5FLOONGARCH=5FPNX 6 > +=23define EXCEPT=5FLOONGARCH=5FPPI 7 > +=23define EXCEPT=5FLOONGARCH=5FADE 8 > +=23define EXCEPT=5FLOONGARCH=5FALE 9 > +=23define EXCEPT=5FLOONGARCH=5FBCE 10 > +=23define EXCEPT=5FLOONGARCH=5FSYS 11 > +=23define EXCEPT=5FLOONGARCH=5FBRK 12 > +=23define EXCEPT=5FLOONGARCH=5FINE 13 > +=23define EXCEPT=5FLOONGARCH=5FIPE 14 > +=23define EXCEPT=5FLOONGARCH=5F=46PD 15 > +=23define EXCEPT=5FLOONGARCH=5FSXD 16 > +=23define EXCEPT=5FLOONGARCH=5FASXD 17 > +=23define EXCEPT=5FLOONGARCH=5F=46PE 18 > +=23define EXCEPT=5FLOONGARCH=5FTBR 64 // =46or code only, there is no = such type in the ISA spec, the TLB refill is defined for an independent e= xception. > + > +// > +// LoongArch processor Interrupt types. > +// > +=23define EXCEPT=5FLOONGARCH=5FINT=5FSIP0 0 > +=23define EXCEPT=5FLOONGARCH=5FINT=5FSIP1 1 > +=23define EXCEPT=5FLOONGARCH=5FINT=5FIP0 2 > +=23define EXCEPT=5FLOONGARCH=5FINT=5FIP1 3 > +=23define EXCEPT=5FLOONGARCH=5FINT=5FIP2 4 > +=23define EXCEPT=5FLOONGARCH=5FINT=5FIP3 5 > +=23define EXCEPT=5FLOONGARCH=5FINT=5FIP4 6 > +=23define EXCEPT=5FLOONGARCH=5FINT=5FIP5 7 > +=23define EXCEPT=5FLOONGARCH=5FINT=5FIP6 8 > +=23define EXCEPT=5FLOONGARCH=5FINT=5FIP7 9 > +=23define EXCEPT=5FLOONGARCH=5FINT=5FPMC 10 > +=23define EXCEPT=5FLOONGARCH=5FINT=5FTIMER 11 > +=23define EXCEPT=5FLOONGARCH=5FINT=5FIPI 12 > + > +// > +// =46or coding convenience, define the maximum valid > +// LoongArch interrupt. > +// > +=23define MAX=5FLOONGARCH=5FINTERRUPT 14 > + > +typedef struct =7B > + UINT64 R0; > + UINT64 R1; > + UINT64 R2; > + UINT64 R3; > + UINT64 R4; > + UINT64 R5; > + UINT64 R6; > + UINT64 R7; > + UINT64 R8; > + UINT64 R9; > + UINT64 R10; > + UINT64 R11; > + UINT64 R12; > + UINT64 R13; > + UINT64 R14; > + UINT64 R15; > + UINT64 R16; > + UINT64 R17; > + UINT64 R18; > + UINT64 R19; > + UINT64 R20; > + UINT64 R21; > + UINT64 R22; > + UINT64 R23; > + UINT64 R24; > + UINT64 R25; > + UINT64 R26; > + UINT64 R27; > + UINT64 R28; > + UINT64 R29; > + UINT64 R30; > + UINT64 R31; > + > + UINT64 CRMD; // CuRrent MoDe information > + UINT64 PRMD; // PRe-exception MoDe information > + UINT64 EUEN; // Extended component Unit ENable > + UINT64 MISC; // MISCellaneous controller > + UINT64 EC=46G; // Exception Con=46iGuration > + UINT64 ESTAT; // Exception STATus > + UINT64 ERA; // Exception Return Address > + UINT64 BADV; // BAD Virtual address > + UINT64 BADI; // BAD Instruction > +=7D E=46I=5FSYSTEM=5FCONTEXT=5FLOONGARCH64; > + > /// > /// Universal E=46I=5FSYSTEM=5FCONTEXT definition. > /// > typedef union =7B > - E=46I=5FSYSTEM=5FCONTEXT=5FEBC *SystemContextEbc; > - E=46I=5FSYSTEM=5FCONTEXT=5FIA32 *SystemContextIa32; > - E=46I=5FSYSTEM=5FCONTEXT=5FX64 *SystemContextX64; > - E=46I=5FSYSTEM=5FCONTEXT=5FIP=46 *SystemContextIpf; > - E=46I=5FSYSTEM=5FCONTEXT=5FARM *SystemContextArm; > - E=46I=5FSYSTEM=5FCONTEXT=5FAARCH64 *SystemContextAArch64; > - E=46I=5FSYSTEM=5FCONTEXT=5FRISCV64 *SystemContextRiscV64; > + E=46I=5FSYSTEM=5FCONTEXT=5FEBC *SystemContextEbc; > + E=46I=5FSYSTEM=5FCONTEXT=5FIA32 *SystemContextIa32; > + E=46I=5FSYSTEM=5FCONTEXT=5FX64 *SystemContextX64; > + E=46I=5FSYSTEM=5FCONTEXT=5FIP=46 *SystemContextIpf; > + E=46I=5FSYSTEM=5FCONTEXT=5FARM *SystemContextArm; > + E=46I=5FSYSTEM=5FCONTEXT=5FAARCH64 *SystemContextAArch64; > + E=46I=5FSYSTEM=5FCONTEXT=5FRISCV64 *SystemContextRiscV64; > + E=46I=5FSYSTEM=5FCONTEXT=5FLOONGARCH64 *SystemContextLoongArch64; > =7D E=46I=5FSYSTEM=5FCONTEXT; > > > // > diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Pro= tocol/PxeBaseCode.h > index 11872d602d..6787941a5d 100644 > --- a/MdePkg/Include/Protocol/PxeBaseCode.h > +++ b/MdePkg/Include/Protocol/PxeBaseCode.h > =40=40 -4,6 +4,7 =40=40 > > > Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
> Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
> +Copyright (c) 2022, Loongson Technology Corporation Limited. All right= s reserved.
> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > =40=40 -158,6 +159,8 =40=40 typedef UINT16 E=46I=5FPXE=5FBASE=5FCODE=5F= UDP=5FPORT; > =23define E=46I=5FPXE=5FCLIENT=5FSYSTEM=5FARCHITECTURE 0x000B > > =23elif defined (MDE=5FCPU=5FRISCV64) > =23define E=46I=5FPXE=5FCLIENT=5FSYSTEM=5FARCHITECTURE 0x001B > +=23elif defined (MDE=5FCPU=5FLOONGARCH64) > +=23define E=46I=5FPXE=5FCLIENT=5FSYSTEM=5FARCHITECTURE 0x0027 > =23endif > > > /// > diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/U= efiBaseType.h > index 4a34ce8e25..83975a08eb 100644 > --- a/MdePkg/Include/Uefi/UefiBaseType.h > +++ b/MdePkg/Include/Uefi/UefiBaseType.h > =40=40 -4,6 +4,7 =40=40 > Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
> > Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
> Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
> +Copyright (c) 2022, Loongson Technology Corporation Limited. All right= s reserved.
> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > =40=40 -246,6 +247,12 =40=40 typedef union =7B > =23define E=46I=5FIMAGE=5FMACHINE=5FRISCV64 0x5064 > > =23define E=46I=5FIMAGE=5FMACHINE=5FRISCV128 0x5128 > > > +/// > +/// PE32+ Machine type for LoongArch 32/64 images. > +/// > +=23define E=46I=5FIMAGE=5FMACHINE=5FLOONGARCH32 0x6232 > +=23define E=46I=5FIMAGE=5FMACHINE=5FLOONGARCH64 0x6264 > + > =23if =21defined (E=46I=5FIMAGE=5FMACHINE=5FTYPE=5FVALUE) && =21defined= (E=46I=5FIMAGE=5FMACHINE=5FCROSS=5FTYPE=5FVALUE) > =23if defined (MDE=5FCPU=5FIA32) > > > =40=40 -278,6 +285,13 =40=40 typedef union =7B > =23define E=46I=5FIMAGE=5FMACHINE=5FTYPE=5FSUPPORTED(Machine) =5C > > ((Machine) =3D=3D E=46I=5FIMAGE=5FMACHINE=5FRISCV64) > > > +=23define E=46I=5FIMAGE=5FMACHINE=5FCROSS=5FTYPE=5FSUPPORTED(Machine) = (=46ALSE) > + > + =23elif defined (MDE=5FCPU=5FLOONGARCH64) > + > +=23define E=46I=5FIMAGE=5FMACHINE=5FTYPE=5FSUPPORTED(Machine) =5C > + ((Machine) =3D=3D E=46I=5FIMAGE=5FMACHINE=5FLOONGARCH64) > + > =23define E=46I=5FIMAGE=5FMACHINE=5FCROSS=5FTYPE=5FSUPPORTED(Machine) (= =46ALSE) > > > =23elif defined (MDE=5FCPU=5FEBC) > diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiS= pec.h > index 2b38b100f6..3abebbb8d9 100644 > --- a/MdePkg/Include/Uefi/UefiSpec.h > +++ b/MdePkg/Include/Uefi/UefiSpec.h > =40=40 -7,6 +7,7 =40=40 > > > Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
> Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP.= All rights reserved.
> +Copyright (c) 2022, Loongson Technology Corporation Limited. All right= s reserved.
> > > SPDX-License-Identifier: BSD-2-Clause-Patent > > > =40=40 -2195,12 +2196,13 =40=40 typedef struct =7B > // > > // E=46I =46ile location to boot from on removable media devices > // > -=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FIA32 L=22=5C=5CE= =46I=5C=5CBOOT=5C=5CBOOTIA32.E=46I=22 > -=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FIA64 L=22=5C=5CE= =46I=5C=5CBOOT=5C=5CBOOTIA64.E=46I=22 > -=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FX64 L=22=5C=5CE=46= I=5C=5CBOOT=5C=5CBOOTX64.E=46I=22 > -=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FARM L=22=5C=5CE=46= I=5C=5CBOOT=5C=5CBOOTARM.E=46I=22 > -=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FAARCH64 L=22=5C=5C= E=46I=5C=5CBOOT=5C=5CBOOTAA64.E=46I=22 > -=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FRISCV64 L=22=5C=5C= E=46I=5C=5CBOOT=5C=5CBOOTRISCV64.E=46I=22 > +=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FIA32 L=22=5C=5CE= =46I=5C=5CBOOT=5C=5CBOOTIA32.E=46I=22 > +=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FIA64 L=22=5C=5CE= =46I=5C=5CBOOT=5C=5CBOOTIA64.E=46I=22 > +=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FX64 L=22=5C=5CE=46= I=5C=5CBOOT=5C=5CBOOTX64.E=46I=22 > +=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FARM L=22=5C=5CE=46= I=5C=5CBOOT=5C=5CBOOTARM.E=46I=22 > +=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FAARCH64 L=22=5C=5C= E=46I=5C=5CBOOT=5C=5CBOOTAA64.E=46I=22 > +=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FRISCV64 L=22=5C=5C= E=46I=5C=5CBOOT=5C=5CBOOTRISCV64.E=46I=22 > +=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FLOONGARCH64 L=22= =5C=5CE=46I=5C=5CBOOT=5C=5CBOOTLOONGARCH64.E=46I=22 > > > =23if =21defined (E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME) > =23if defined (MDE=5FCPU=5FIA32) > =40=40 -2214,6 +2216,8 =40=40 typedef struct =7B > =23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME E=46I=5FREMOVABLE=5F= MEDIA=5F=46ILE=5FNAME=5FAARCH64 > > =23elif defined (MDE=5FCPU=5FRISCV64) > =23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME E=46I=5FREMOVABLE=5F= MEDIA=5F=46ILE=5FNAME=5FRISCV64 > + =23elif defined (MDE=5FCPU=5FLOONGARCH64) > +=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME E=46I=5FREMOVABLE=5F= MEDIA=5F=46ILE=5FNAME=5FLOONGARCH64 > =23else > =23error Unknown Processor Type > =23endif > -- > 2.27.0 > --632d5318_623fd81b_dbe1 Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline
Hi Mike,
In the V2, I added IANA, Microsoft and UE=46I spe= cification links in every patches that uses them. Associated patches:

0008-MdePkg-Include-Add-LOONGARCH-related-definitions-= .patch
0015-BaseToo= ls-BaseTools-changes-for-LoongArch-platfor.patch
0022-MdePkg-Include-LoongArch-definitions.p= atch(This patch)
=
Please check and review them again.


= Thanks,
Chao
--------

On 9=E6=9C=88 14 2022, at 5:41 =E4=B8=8B=E5= =8D=88, Chao Li <lichao=40loongson.cn> wrote:
RE=46: https://bugzilla.tianocore.org/show=5Fbug.cgi=3Fid=3D4053
Add LoongArch processor related definitions.

=46= or the Http boot and PXE boot types seeing this URL section =22Processor<= /div>
Architecture Type=22 for the LOONGARCH values:
https:= //www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml
=46or definitions of PE/CO=46=46 and LOONGARCH relocation types= , see the
=22Machine Types=22 and =22Basic Relocation Types=22 = sections of this URL for
LOONGARCH values:
https://do= cs.microsoft.com/en-us/windows/win32/debug/pe-format

=46or = the register definitions of exceptions context, see the UE=46I V2.10
18.2.2, 18.2.4 and 18.2.5 sections of this URL for LOONGARCH
<= div>definitions:
https://uefi.org/specs/UE=46I/2.10/18=5FProtoc= ols=5FDebugger=5FSupport.html

Cc: Michael D Kinney <mich= ael.d.kinney=40intel.com>
Cc: Liming Gao <gaoliming=40byo= soft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu=40intel.com&g= t;

Signed-off-by: Chao Li <lichao=40loongson.cn>
---
MdePkg/Include/IndustryStandard/PeImage.h =7C 9 ++
MdePkg/Include/Protocol/DebugSupport.h =7C 107 ++++++++++++++++++= ++--
MdePkg/Include/Protocol/PxeBaseCode.h =7C 3 +
Md= ePkg/Include/Uefi/UefiBaseType.h =7C 14 +++
MdePkg/Include/Uefi= /UefiSpec.h =7C 16 ++--
5 files changed, 136 insertions(+), 13 = deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/P= eImage.h b/MdePkg/Include/IndustryStandard/PeImage.h
index 3109= dc20f8..dd4cc25483 100644
--- a/MdePkg/Include/IndustryStandard= /PeImage.h
+++ b/MdePkg/Include/IndustryStandard/PeImage.h
=40=40 -10,6 +10,7 =40=40
Copyright (c) 2006 - 2018, Inte= l Corporation. All rights reserved.<BR>

Portions copy= right (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Deve= lopment LP. All rights reserved.<BR>

+Portions Copyri= ght (c) 2022, Loongson Technology Corporation Limited. All rights reserve= d.<BR>



SPDX-License-Identifier: BSD-2-Clause-= Patent



=40=40 -38,6 +39,8 =40=40 SPDX-License-Ident= ifier: BSD-2-Clause-Patent
=23define IMAGE=5F=46ILE=5FMACHINE=5F= RISCV32 0x5032

=23define IMAGE=5F=46ILE=5FMACHINE=5FRISCV64= 0x5064

=23define IMAGE=5F=46ILE=5FMACHINE=5FRISCV128 0x512= 8

+=23define IMAGE=5F=46ILE=5FMACHINE=5FLOONGARCH32 0x6232<= /div>
+=23define IMAGE=5F=46ILE=5FMACHINE=5FLOONGARCH64 0x6264


//

// EXE file formats

=40= =40 -503,6 +506,12 =40=40 typedef struct =7B
=23define E=46I=5F= IMAGE=5FREL=5FBASED=5FRISCV=5FLOW12I 7

=23define E=46I=5FIM= AGE=5FREL=5FBASED=5FRISCV=5FLOW12S 8



+//

<= div>+// Relocation types of LoongArch processor.

+//
<= br>
+=23define E=46I=5FIMAGE=5FREL=5FBASED=5FLOONGARCH32=5FMARK=5FLA = 8

+=23define E=46I=5FIMAGE=5FREL=5FBASED=5FLOONGARCH64=5FMA= RK=5FLA 8

+

///

/// Line number= format.

///

diff --git a/MdePkg/Include/Prot= ocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h
in= dex ec5b92a5c5..2b0ae2d157 100644
--- a/MdePkg/Include/Protocol= /DebugSupport.h
+++ b/MdePkg/Include/Protocol/DebugSupport.h
=40=40 -654,17 +654,110 =40=40 typedef struct =7B
UINT6= 4 X31;

=7D E=46I=5FSYSTEM=5FCONTEXT=5FRISCV64;


+//

+// LoongArch processor exception types.
+//

+=23define EXCEPT=5FLOONGARCH=5FINT 0
+=23define EXCEPT=5FLOONGARCH=5FPIL 1

+=23define EXC= EPT=5FLOONGARCH=5FPIS 2

+=23define EXCEPT=5FLOONGARCH=5FPI=46= 3

+=23define EXCEPT=5FLOONGARCH=5FPME 4

+=23= define EXCEPT=5FLOONGARCH=5FPNR 5

+=23define EXCEPT=5FLOONG= ARCH=5FPNX 6

+=23define EXCEPT=5FLOONGARCH=5FPPI 7
+=23define EXCEPT=5FLOONGARCH=5FADE 8

+=23define EXCE= PT=5FLOONGARCH=5FALE 9

+=23define EXCEPT=5FLOONGARCH=5FBCE = 10

+=23define EXCEPT=5FLOONGARCH=5FSYS 11

+=23= define EXCEPT=5FLOONGARCH=5FBRK 12

+=23define EXCEPT=5FLOON= GARCH=5FINE 13

+=23define EXCEPT=5FLOONGARCH=5FIPE 14
=
+=23define EXCEPT=5FLOONGARCH=5F=46PD 15

+=23defin= e EXCEPT=5FLOONGARCH=5FSXD 16

+=23define EXCEPT=5FLOONGARCH= =5FASXD 17

+=23define EXCEPT=5FLOONGARCH=5F=46PE 18
+=23define EXCEPT=5FLOONGARCH=5FTBR 64 // =46or code only, there i= s no such type in the ISA spec, the TLB refill is defined for an independ= ent exception.

+

+//

+// LoongA= rch processor Interrupt types.

+//

+=23define= EXCEPT=5FLOONGARCH=5FINT=5FSIP0 0

+=23define EXCEPT=5FLOON= GARCH=5FINT=5FSIP1 1

+=23define EXCEPT=5FLOONGARCH=5FINT=5F= IP0 2

+=23define EXCEPT=5FLOONGARCH=5FINT=5FIP1 3

=
+=23define EXCEPT=5FLOONGARCH=5FINT=5FIP2 4

+=23define= EXCEPT=5FLOONGARCH=5FINT=5FIP3 5

+=23define EXCEPT=5FLOONG= ARCH=5FINT=5FIP4 6

+=23define EXCEPT=5FLOONGARCH=5FINT=5FIP= 5 7

+=23define EXCEPT=5FLOONGARCH=5FINT=5FIP6 8

+=23define EXCEPT=5FLOONGARCH=5FINT=5FIP7 9

+=23define E= XCEPT=5FLOONGARCH=5FINT=5FPMC 10

+=23define EXCEPT=5FLOONGA= RCH=5FINT=5FTIMER 11

+=23define EXCEPT=5FLOONGARCH=5FINT=5F= IPI 12

+

+//

+// =46or coding c= onvenience, define the maximum valid

+// LoongArch interrup= t.

+//

+=23define MAX=5FLOONGARCH=5FINTERRUPT= 14

+

+typedef struct =7B

+ UIN= T64 R0;

+ UINT64 R1;

+ UINT64 R2;

+ UINT64 R3;

+ UINT64 R4;

+ UINT64 R5;
+ UINT64 R6;

+ UINT64 R7;

+ UINT64= R8;

+ UINT64 R9;

+ UINT64 R10;

+ UINT64 R11;

+ UINT64 R12;

+ UINT64 R13;
+ UINT64 R14;

+ UINT64 R15;

+ UIN= T64 R16;

+ UINT64 R17;

+ UINT64 R18;
+ UINT64 R19;

+ UINT64 R20;

+ UINT64 R2= 1;

+ UINT64 R22;

+ UINT64 R23;

= + UINT64 R24;

+ UINT64 R25;

+ UINT64 R26;
+ UINT64 R27;

+ UINT64 R28;

+ UINT= 64 R29;

+ UINT64 R30;

+ UINT64 R31;

=
+

+ UINT64 CRMD; // CuRrent MoDe information

=
+ UINT64 PRMD; // PRe-exception MoDe information

+ UIN= T64 EUEN; // Extended component Unit ENable

+ UINT64 MISC; = // MISCellaneous controller

+ UINT64 EC=46G; // Exception C= on=46iGuration

+ UINT64 ESTAT; // Exception STATus
+ UINT64 ERA; // Exception Return Address

+ UINT64 BA= DV; // BAD Virtual address

+ UINT64 BADI; // BAD Instructio= n

+=7D E=46I=5FSYSTEM=5FCONTEXT=5FLOONGARCH64;

+

///

/// Universal E=46I=5FSYSTEM=5FCONTEX= T definition.

///

typedef union =7B

=
- E=46I=5FSYSTEM=5FCONTEXT=5FEBC *SystemContextEbc;

- = E=46I=5FSYSTEM=5FCONTEXT=5FIA32 *SystemContextIa32;

- E=46I= =5FSYSTEM=5FCONTEXT=5FX64 *SystemContextX64;

- E=46I=5FSYST= EM=5FCONTEXT=5FIP=46 *SystemContextIpf;

- E=46I=5FSYSTEM=5F= CONTEXT=5FARM *SystemContextArm;

- E=46I=5FSYSTEM=5FCONTEXT= =5FAARCH64 *SystemContextAArch64;

- E=46I=5FSYSTEM=5FCONTEX= T=5FRISCV64 *SystemContextRiscV64;

+ E=46I=5FSYSTEM=5FCONTE= XT=5FEBC *SystemContextEbc;

+ E=46I=5FSYSTEM=5FCONTEXT=5FIA= 32 *SystemContextIa32;

+ E=46I=5FSYSTEM=5FCONTEXT=5FX64 *Sy= stemContextX64;

+ E=46I=5FSYSTEM=5FCONTEXT=5FIP=46 *SystemC= ontextIpf;

+ E=46I=5FSYSTEM=5FCONTEXT=5FARM *SystemContextA= rm;

+ E=46I=5FSYSTEM=5FCONTEXT=5FAARCH64 *SystemContextAArc= h64;

+ E=46I=5FSYSTEM=5FCONTEXT=5FRISCV64 *SystemContextRis= cV64;

+ E=46I=5FSYSTEM=5FCONTEXT=5FLOONGARCH64 *SystemConte= xtLoongArch64;

=7D E=46I=5FSYSTEM=5FCONTEXT;


<= br>
//

diff --git a/MdePkg/Include/Protocol/PxeBaseCode= .h b/MdePkg/Include/Protocol/PxeBaseCode.h
index 11872d602d..67= 87941a5d 100644
--- a/MdePkg/Include/Protocol/PxeBaseCode.h
+++ b/MdePkg/Include/Protocol/PxeBaseCode.h
=40=40 -4,6 = +4,7 =40=40


Copyright (c) 2006 - 2018, Intel Corporatio= n. All rights reserved.<BR>

Copyright (c) 2020, Hewle= tt Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2022, Loongson Technology Corporation Limited. A= ll rights reserved.<BR>



SPDX-License-Identifi= er: BSD-2-Clause-Patent



=40=40 -158,6 +159,8 =40=40= typedef UINT16 E=46I=5FPXE=5FBASE=5FCODE=5FUDP=5FPORT;
=23defi= ne E=46I=5FPXE=5FCLIENT=5FSYSTEM=5FARCHITECTURE 0x000B

=23e= lif defined (MDE=5FCPU=5FRISCV64)

=23define E=46I=5FPXE=5FC= LIENT=5FSYSTEM=5FARCHITECTURE 0x001B

+=23elif defined (MDE=5F= CPU=5FLOONGARCH64)

+=23define E=46I=5FPXE=5FCLIENT=5FSYSTEM= =5FARCHITECTURE 0x0027

=23endif



///
diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Inc= lude/Uefi/UefiBaseType.h
index 4a34ce8e25..83975a08eb 100644
--- a/MdePkg/Include/Uefi/UefiBaseType.h
+++ b/MdePkg/I= nclude/Uefi/UefiBaseType.h
=40=40 -4,6 +4,7 =40=40
Co= pyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>= ;

Portions copyright (c) 2011 - 2016, ARM Ltd. All rights r= eserved.<BR>

Copyright (c) 2020, Hewlett Packard Ente= rprise Development LP. All rights reserved.<BR>

+Copy= right (c) 2022, Loongson Technology Corporation Limited. All rights reser= ved.<BR>



SPDX-License-Identifier: BSD-2-Claus= e-Patent



=40=40 -246,6 +247,12 =40=40 typedef union= =7B
=23define E=46I=5FIMAGE=5FMACHINE=5FRISCV64 0x5064
=23define E=46I=5FIMAGE=5FMACHINE=5FRISCV128 0x5128


<= br>
+///

+/// PE32+ Machine type for LoongArch 32/64 im= ages.

+///

+=23define E=46I=5FIMAGE=5FMACHINE= =5FLOONGARCH32 0x6232

+=23define E=46I=5FIMAGE=5FMACHINE=5F= LOONGARCH64 0x6264

+

=23if =21defined (E=46I=5F= IMAGE=5FMACHINE=5FTYPE=5FVALUE) && =21defined (E=46I=5FIMAGE=5FMA= CHINE=5FCROSS=5FTYPE=5FVALUE)

=23if defined (MDE=5FCPU=5FIA= 32)



=40=40 -278,6 +285,13 =40=40 typedef union =7B<= /div>
=23define E=46I=5FIMAGE=5FMACHINE=5FTYPE=5FSUPPORTED(Machine) =5C=

((Machine) =3D=3D E=46I=5FIMAGE=5FMACHINE=5FRISCV64)
=


+=23define E=46I=5FIMAGE=5FMACHINE=5FCROSS=5FTYPE=5FSUPP= ORTED(Machine) (=46ALSE)

+

+ =23elif defined = (MDE=5FCPU=5FLOONGARCH64)

+

+=23define E=46I=5F= IMAGE=5FMACHINE=5FTYPE=5FSUPPORTED(Machine) =5C

+ ((Machine= ) =3D=3D E=46I=5FIMAGE=5FMACHINE=5FLOONGARCH64)

+

=
=23define E=46I=5FIMAGE=5FMACHINE=5FCROSS=5FTYPE=5FSUPPORTED(Machine= ) (=46ALSE)



=23elif defined (MDE=5FCPU=5FEBC)
=
diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uef= i/UefiSpec.h
index 2b38b100f6..3abebbb8d9 100644
--- = a/MdePkg/Include/Uefi/UefiSpec.h
+++ b/MdePkg/Include/Uefi/Uefi= Spec.h
=40=40 -7,6 +7,7 =40=40


Copyright (c) = 2006 - 2021, Intel Corporation. All rights reserved.<BR>

<= div>Portions Copyright (c) 2020, Hewlett Packard Enterprise Development L= P. All rights reserved.<BR>

+Copyright (c) 2022, Loon= gson Technology Corporation Limited. All rights reserved.<BR>
=


SPDX-License-Identifier: BSD-2-Clause-Patent


=40=40 -2195,12 +2196,13 =40=40 typedef struct =7B
/= /

// E=46I =46ile location to boot from on removable media = devices

//

-=23define E=46I=5FREMOVABLE=5FMED= IA=5F=46ILE=5FNAME=5FIA32 L=22=5C=5CE=46I=5C=5CBOOT=5C=5CBOOTIA32.E=46I=22=

-=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FIA6= 4 L=22=5C=5CE=46I=5C=5CBOOT=5C=5CBOOTIA64.E=46I=22

-=23defi= ne E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FX64 L=22=5C=5CE=46I=5C=5CB= OOT=5C=5CBOOTX64.E=46I=22

-=23define E=46I=5FREMOVABLE=5FME= DIA=5F=46ILE=5FNAME=5FARM L=22=5C=5CE=46I=5C=5CBOOT=5C=5CBOOTARM.E=46I=22=

-=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FAAR= CH64 L=22=5C=5CE=46I=5C=5CBOOT=5C=5CBOOTAA64.E=46I=22

-=23d= efine E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FRISCV64 L=22=5C=5CE=46I= =5C=5CBOOT=5C=5CBOOTRISCV64.E=46I=22

+=23define E=46I=5FREM= OVABLE=5FMEDIA=5F=46ILE=5FNAME=5FIA32 L=22=5C=5CE=46I=5C=5CBOOT=5C=5CBOOT= IA32.E=46I=22

+=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE= =5FNAME=5FIA64 L=22=5C=5CE=46I=5C=5CBOOT=5C=5CBOOTIA64.E=46I=22

=
+=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FX64 L=22=5C=5C= E=46I=5C=5CBOOT=5C=5CBOOTX64.E=46I=22

+=23define E=46I=5FRE= MOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FARM L=22=5C=5CE=46I=5C=5CBOOT=5C=5CBOOT= ARM.E=46I=22

+=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5F= NAME=5FAARCH64 L=22=5C=5CE=46I=5C=5CBOOT=5C=5CBOOTAA64.E=46I=22

=
+=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FRISCV64 L=22=5C= =5CE=46I=5C=5CBOOT=5C=5CBOOTRISCV64.E=46I=22

+=23define E=46= I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FLOONGARCH64 L=22=5C=5CE=46I=5C=5C= BOOT=5C=5CBOOTLOONGARCH64.E=46I=22



=23if =21defined= (E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME)

=23if defined = (MDE=5FCPU=5FIA32)

=40=40 -2214,6 +2216,8 =40=40 typedef st= ruct =7B
=23define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME E=46= I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FAARCH64

=23elif def= ined (MDE=5FCPU=5FRISCV64)

=23define E=46I=5FREMOVABLE=5FME= DIA=5F=46ILE=5FNAME E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME=5FRISCV64
+ =23elif defined (MDE=5FCPU=5FLOONGARCH64)

+=23= define E=46I=5FREMOVABLE=5FMEDIA=5F=46ILE=5FNAME E=46I=5FREMOVABLE=5FMEDI= A=5F=46ILE=5FNAME=5FLOONGARCH64

=23else

=23er= ror Unknown Processor Type

=23endif

--
<= div>2.27.0
--632d5318_623fd81b_dbe1--