Re: [edk2-devel] question about PCI bridge's bus range window configure's save and restore

Re: [edk2-devel] question about PCI bridge's bus range window configure's save and restore

[Tiger Liu(BJ-RD)]

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Hi, Ric:
Thanks for your reply.

I think maybe some standard PCI config space registers, such as BAR registers, its content is restored by OS during S3 resume procedure.

Such as:
PCI bus driver scans PCI bus and assigns every PCI device’s resource requirements, and sets these BAR registers.
But PCI bus driver doesn’t save these BAR configurations into Boot Script.

So, I think PCI bridges’ secondary bus number / subordinate bus number registers are all standard PCI bridge’s config space registers.
Maybe OS will also restore its original setting.

Thanks
发件人: Ric Wang (王晓) <wangxiao.bj@inspur.com>
发送时间: 2020年8月10日 19:55
收件人: devel@edk2.groups.io; Tiger Liu(BJ-RD) <TigerLiu@zhaoxin.com>
主题: 答复: [edk2-devel] question about PCI bridge's bus range window configure's save and restore

It’s done by BIOS pei s3 resume code.  Restored register value saved  while BIOS normal POST BY BootScriptExecutor.  You can refer  gEfiPeiS3Resume2Ppi  usage
Thanks
发件人: devel@edk2.groups.io<mailto:devel@edk2.groups.io> [mailto:devel@edk2.groups.io] 代表 Tiger Liu(BJ-RD)
发送时间: 2020年8月10日 17:32
收件人: devel@edk2.groups.io<mailto:devel@edk2.groups.io>
主题: [edk2-devel] question about PCI bridge's bus range window configure's save and restore

Hi, Experts:
I have a question about PCI Bridge’s config space’s save and restore.

Pci bus driver configured PCI Bridges’ secondary bus number register and subordinate bus number register.

So, if system resumes from S3(Suspend to ram) state, who is responsible for restoring PCI Bridges’ secondary bus number / subordinate bus number registers’ content?

Will the OS be responsible for it?

Thanks


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[edk2-devel] question about PCI bridge's bus range window configure's save and restore

[Tiger Liu(BJ-RD)]

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Hi, Experts:
I have a question about PCI Bridge’s config space’s save and restore.

Pci bus driver configured PCI Bridges’ secondary bus number register and subordinate bus number register.

So, if system resumes from S3(Suspend to ram) state, who is responsible for restoring PCI Bridges’ secondary bus number / subordinate bus number registers’ content?

Will the OS be responsible for it?

Thanks



保密声明：
本邮件含有保密或专有信息，仅供指定收件人使用。严禁对本邮件或其内容做任何未经授权的查阅、使用、复制或转发。
CONFIDENTIAL NOTE:
This email contains confidential or legally privileged information and is for the sole use of its intended recipient. Any unauthorized review, use, copying or forwarding of this email or the content of this email is strictly prohibited.

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