From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::542; helo=mail-pg1-x542.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 278342097F551 for ; Wed, 25 Jul 2018 19:17:27 -0700 (PDT) Received: by mail-pg1-x542.google.com with SMTP id a11-v6so122244pgw.6 for ; Wed, 25 Jul 2018 19:17:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-transfer-encoding; bh=OE2GSGHqRhbVe4DpREmwMWOey+7Ni8rmsIC11XP9/l0=; b=ezTTyK3C27XbkWTN0dvzbJlz5az7QshM7L/7LO8X6DK8sgqaODi+ZjLHzEZIj7Od+Y vtJVuTe8DvkwvpuVpy+XAhOS+PfxLsHnBuX3BPWdJaeEveIws0isQKlbcQCNvUafbCKs tkr6P0a5XUJHdickQs7gZYpKLfCdNnnEz130o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-transfer-encoding; bh=OE2GSGHqRhbVe4DpREmwMWOey+7Ni8rmsIC11XP9/l0=; b=exVEog6hGdSKZD/2tQdWBgYznhj/Ta5UpmAIOmeVFByVxHaAoJWtoKxkQut9/3ThaN QT9Qmh9DHNXXF0FYVy6QRSAOAegUx6U1cdVzYKDMDOZhKZm2ATKIPB52diRzd8PBETub he5lvfWt6K7Y8ebL3emzZHRNYoX4WOwiTqngweufnq3oTRthqGzQ68L5YM/8cPIhuSdr 8L7QfSdl4OPulGDooIGGHTEsKS8vrVFG74pJSQnMq7fE374DbYR2VqarIxydhb+Wgzh3 qFfo7XaobyOshuortF+uWy7glKp1rsncKRV2UUUZJbHc8CdBeuCtz+EPjCg7yWZtqWlF 5bQQ== X-Gm-Message-State: AOUpUlFItTgcvu4ZFv2JH32Hyo4HiYtNUy/QHBuZPcAPKOy1ZcuP+D2l X7ir2VRNH+9kIP2kqmnfBjIBjA== X-Google-Smtp-Source: AAOMgpesISxb4rvhJkUIPvX9mRkAMCB+IInFLI2gr/FYLzrTnkK6mTrlNQ//TQrb7hP6ATZDHli74w== X-Received: by 2002:a63:3c0c:: with SMTP id j12-v6mr57290pga.440.1532571447651; Wed, 25 Jul 2018 19:17:27 -0700 (PDT) Received: from [10.165.0.110] ([64.64.108.191]) by smtp.gmail.com with ESMTPSA id r83-v6sm82853pgr.8.2018.07.25.19.17.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 25 Jul 2018 19:17:27 -0700 (PDT) To: Ard Biesheuvel , liudongdong3@huawei.com Cc: Leif Lindholm , linaro-uefi , "edk2-devel@lists.01.org" , Graeme Gregory , guoheyi@huawei.com, wanghuiqiang , huangming , Jason Zhang , huangdaode@hisilicon.com, John Garry , Heyi Guo References: <20180713081540.8414-1-ming.huang@linaro.org> <20180713081540.8414-5-ming.huang@linaro.org> From: Ming Message-ID: <0b31813f-8166-c27e-a593-25bb42ea2f91@linaro.org> Date: Thu, 26 Jul 2018 10:17:15 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 MIME-Version: 1.0 In-Reply-To: Subject: Re: [PATCH edk2-platforms v3 4/6] Hisilicon/D05: Add PlatformMiscDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jul 2018 02:17:28 -0000 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit 在 7/25/2018 6:51 PM, Ard Biesheuvel 写道: > On 13 July 2018 at 10:15, Ming Huang wrote: >> Fix the issue of onboard Nic not work kerenl with AMD GPU and >> NVME SSD in board. The GPU don't support 64 MSI, so need to >> allocate INTx, but the default interrupt number 255 is invalid, >> so Change all the PCI Device interrupt number to 0. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Ming Huang >> Signed-off-by: Heyi Guo > > I don't understand why this issue is specific to this platform. > > Can you explain in more detail what the failure mode is, and why > setting the PCI interrupt line is necessary here, while it doesn't > seem to be on other platforms, even when falling back to INTx > interrupts? > I don't know exactly why setting the PCI interrupt line is necessary in uefi. This issue is analyzed by kernel guy DongDong.Liu. @DongDong, Can you explain the questions? Thanks. >> --- >> Platform/Hisilicon/D05/D05.dsc | 1 + >> Platform/Hisilicon/D05/D05.fdf | 1 + >> Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99 ++++++++++++++++++++ >> Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47 ++++++++++ >> 4 files changed, 148 insertions(+) >> >> diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc >> index b6e1a9d98a..0e6d5912a0 100644 >> --- a/Platform/Hisilicon/D05/D05.dsc >> +++ b/Platform/Hisilicon/D05/D05.dsc >> @@ -629,6 +629,7 @@ >> >> >> Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf >> + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf >> >> # >> # Memory test >> diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf >> index 4503776d63..61e8d907f9 100644 >> --- a/Platform/Hisilicon/D05/D05.fdf >> +++ b/Platform/Hisilicon/D05/D05.fdf >> @@ -354,6 +354,7 @@ READ_LOCK_STATUS = TRUE >> INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf >> INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf >> INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf >> + INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf >> >> INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf >> >> diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c >> new file mode 100644 >> index 0000000000..8519b7139d >> --- /dev/null >> +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c >> @@ -0,0 +1,99 @@ >> +/** @file >> +* >> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. >> +* Copyright (c) 2016, Linaro Limited. All rights reserved. >> +* >> +* This program and the accompanying materials >> +* are licensed and made available under the terms and conditions of the BSD License >> +* which accompanies this distribution. The full text of the license may be found at >> +* http://opensource.org/licenses/bsd-license.php >> +* >> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. >> +* >> +**/ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +VOID >> +SetIntLine ( >> + ) >> +{ >> + EFI_STATUS Status; >> + UINTN HandleIndex; >> + EFI_HANDLE *HandleBuffer; >> + UINTN HandleCount; >> + EFI_PCI_IO_PROTOCOL *PciIo; >> + UINT8 INTLine; >> + UINTN Segment; >> + UINTN Bus; >> + UINTN Device; >> + UINTN Fun; >> + >> + Status = gBS->LocateHandleBuffer ( >> + ByProtocol, >> + &gEfiPciIoProtocolGuid, >> + NULL, >> + &HandleCount, >> + &HandleBuffer >> + ); >> + if (EFI_ERROR (Status)) { >> + DEBUG ((DEBUG_ERROR, " Locate gEfiPciIoProtocol Failed.\n")); >> + gBS->FreePool ((VOID *)HandleBuffer); >> + return; >> + } >> + >> + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { >> + Status = gBS->HandleProtocol ( >> + HandleBuffer[HandleIndex], >> + &gEfiPciIoProtocolGuid, >> + (VOID **)&PciIo >> + ); >> + if (EFI_ERROR (Status)) { >> + continue; >> + } >> + >> + INTLine = 0; >> + (VOID)PciIo->Pci.Write ( >> + PciIo, >> + EfiPciIoWidthUint8, >> + PCI_INT_LINE_OFFSET, >> + 1, >> + &INTLine); >> + (VOID)PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Fun); >> + DEBUG ((DEBUG_INFO, "Set BDF(%x-%x-%x) IntLine to 0\n", Bus, Device, Fun)); >> + } >> + >> + gBS->FreePool ((VOID *)HandleBuffer); >> + return; >> +} >> + >> +EFI_STATUS >> +EFIAPI >> +PlatformMiscDxeEntry ( >> + IN EFI_HANDLE ImageHandle, >> + IN EFI_SYSTEM_TABLE *SystemTable >> + ) >> +{ >> + EFI_STATUS Status; >> + EFI_EVENT Event; >> + >> + Status = gBS->CreateEventEx ( >> + EVT_NOTIFY_SIGNAL, >> + TPL_CALLBACK, >> + SetIntLine, >> + NULL, >> + &gEfiEventReadyToBootGuid, >> + &Event >> + ); >> + if (EFI_ERROR (Status)) { >> + DEBUG ((DEBUG_ERROR, "Create event for SetIntLine, %r!\n", Status)); >> + } >> + >> + return EFI_SUCCESS; >> +} >> + >> diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf >> new file mode 100644 >> index 0000000000..0b365e7a53 >> --- /dev/null >> +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf >> @@ -0,0 +1,47 @@ >> +#/** @file >> +# >> +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. >> +# Copyright (c) 2016, Linaro Limited. All rights reserved. >> +# >> +# This program and the accompanying materials >> +# are licensed and made available under the terms and conditions of the BSD License >> +# which accompanies this distribution. The full text of the license may be found at >> +# http://opensource.org/licenses/bsd-license.php >> +# >> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. >> +# >> +#**/ >> + >> +[Defines] >> + INF_VERSION = 0x0001001A >> + BASE_NAME = PlatformMiscDxe >> + FILE_GUID = a48f7a09-253f-468b-87c6-caf78baf47bb >> + MODULE_TYPE = DXE_DRIVER >> + VERSION_STRING = 1.0 >> + ENTRY_POINT = PlatformMiscDxeEntry >> + >> +[Sources.common] >> + PlatformMiscDxe.c >> + >> +[Packages] >> + MdeModulePkg/MdeModulePkg.dec >> + MdePkg/MdePkg.dec >> + Silicon/Hisilicon/HisiPkg.dec >> + >> +[Guids] >> + gEfiEventReadyToBootGuid >> + >> +[Protocols] >> + gEfiPciIoProtocolGuid >> + >> +[LibraryClasses] >> + BaseLib >> + DebugLib >> + UefiBootServicesTableLib >> + UefiDriverEntryPoint >> + >> +[FixedPcd] >> + >> +[Depex] >> + TRUE >> -- >> 2.17.0 >>