From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (NAM10-DM6-obe.outbound.protection.outlook.com [40.107.93.76]) by mx.groups.io with SMTP id smtpd.web11.41306.1681125044463503955 for ; Mon, 10 Apr 2023 04:10:44 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@amd.com header.s=selector1 header.b=5LodLqVD; spf=permerror, err=parse error for token &{10 18 %{i}._ip.%{h}._ehlo.%{d}._spf.vali.email}: invalid domain name (domain: amd.com, ip: 40.107.93.76, mailfrom: abdullateef.attar@amd.com) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=clIA3+IJdDvvsQUq8el6/u9yYdiuHW9NZ8jkk152zQe6h1zti/464GYlOunOQAV6KuggJOkc5YVBi8xGrJf7ikZTkZ2Ns02LVkLLu2taZm3jVQMnNGTcgfmvcjCAQfdpIb7Dw0godOQ5Dmyk2cAYNTsyuWn/tzPYELyqeWWvwnxHI05Q6pZFyEZc339AK5S6zobfgVbW00SaW+Am2GD6INOZXEi++EfSmbQGcy0EjCXWUWGGuGaJvjxDV8gC0LprjbcjKq8RgKAL5bNf48NK6cDDjB8UyKIsNhdgNlrYyDaT+VzWOFr1YWAE9LCemKLip4pYDNLe0lbGNV0Dz3xHBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=QbNqmFyB/j3byYSBsXLC5Aew2GOGxScx4j4tfzp0EWg=; b=AZK4vgxEkIqkByvHE/oHohnVI4vFsYpyObpMuEroopV/lNNAeS/xl0mbcUeDevXNnkUmmwGzhEf6QiJAtXoY5oU1c6AUcODZ46c6Sq61ycxb/BEcUdlJqOHB8/lIgWAEpr+o2x1CzlSIan7XM9HCFmSSgSHFFRPSwwxN/sDnG/+OzNiB1OCTVPo/0OUI84XSbL/S9MP5zFBrLpRQjjyiN2JU4eW0EqhgpuUrv5oJbsMA7iqr/sXmZsBabIjZ98dtlRlNK32nf28BGPLWJpXldRrneH3wOp1zBDOPak3RXN15D1W7I1NRNtRvERK/lXY4aJJLPskRWbZBKko1xOiFaQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=edk2.groups.io smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=QbNqmFyB/j3byYSBsXLC5Aew2GOGxScx4j4tfzp0EWg=; b=5LodLqVD0nv54pdbhdUan4alT79TwPC4oUAVR6Rhy/J8FGifmE5TkkswUm8x9AeIg/IxZhrr1B+Nb483s+NKb8DzAkZb6dPGPnPlzlypiKj4ganXbX6TLGEyiKEUDWlLCqmwNPmNtEuFn/4Ubi/ghNi8j7GLIXWw7+AgWGOjJvU= Received: from DM6PR03CA0036.namprd03.prod.outlook.com (2603:10b6:5:40::49) by BN9PR12MB5036.namprd12.prod.outlook.com (2603:10b6:408:135::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6277.34; Mon, 10 Apr 2023 11:10:40 +0000 Received: from DM6NAM11FT067.eop-nam11.prod.protection.outlook.com (2603:10b6:5:40:cafe::3) by DM6PR03CA0036.outlook.office365.com (2603:10b6:5:40::49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6277.35 via Frontend Transport; Mon, 10 Apr 2023 11:10:39 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by DM6NAM11FT067.mail.protection.outlook.com (10.13.172.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6298.25 via Frontend Transport; Mon, 10 Apr 2023 11:10:39 +0000 Received: from SATLEXMB07.amd.com (10.181.41.45) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 10 Apr 2023 06:10:38 -0500 Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB07.amd.com (10.181.41.45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 10 Apr 2023 04:10:19 -0700 Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 10 Apr 2023 06:10:16 -0500 From: "Abdul Lateef Attar" To: CC: Abdul Lateef Attar , Paul Grimes , Garrett Kirkendall , Abner Chang , Eric Dong , Ray Ni , Rahul Kumar , Gerd Hoffmann , Ard Biesheuvel , Jiewen Yao , Jordan Justen Subject: [PATCH v8 8/9] UefiCpuPkg: Uses SmmSmramSaveStateLib library Date: Mon, 10 Apr 2023 16:39:47 +0530 Message-ID: <0bc7e47da753c14dd68fcc1b564e66a44c272aaa.1681121324.git.abdattar@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Return-Path: AbdulLateef.Attar@amd.com X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT067:EE_|BN9PR12MB5036:EE_ X-MS-Office365-Filtering-Correlation-Id: 58ed4c8b-af28-46c2-ed74-08db39b437ee X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4i3tNpE4fjP2AlfLjZYL2pPi0z1sVEXyFYjLBX+VpIh/tLMieGplEwZ9RAWTbaUULCtj9BO8NPoFN3MVCPGMtqZPUnQHDfJT/7M+TIS97MqaIaS6PvvV+UDeyBOka7mz05PN0hLHKNePYrCwA4aljrakzi+zE+3iNSJYbcEMVlJV84E2w2jQJJmUlfOS6P52dYSI+Y8qH04JFyMZqzQFBK0p11dSV4LDSaDBXx1C4w2HUs5dsGDGD/D+NJHJex2xgwvEw+i+tKNqLW3gLWAIr4s5NcBNjD7X48S86RIUh7oaNKUFLbX34Zy5ujtKgfF4BVjiiPDGkj9lJUwaQw9DtoN5iL5vwXfZ4qWQ+BkoMNxK/ABsTKL0X/NMuCTFotM9lNO0r96OaZlO2ERAM+t33GyRKNIjD2NHhCjsdO131ld3PX13S2wsSWkZXYX6Rxo61Mq1JP87eHdPVQGtwc6eL3jbpOeFA6Vs2MlkL4ilCRLHbvsp8p8lA4pv+ImAWhPjLPp57Q7mWGxJDRLmcWk9fgTLP9oV1y8fZQ+b7fi5th04Si8032n1agb19uLUP1hrZalmNRr9vkSPx7ZudVjAMyo87OISKjPFDHLoidgEfyFGizZimKQp+zqKNLNVN3uBCDCcMGqWz20jwIEXutoRG9MWvHm274+3hN9dqHDF2haW3cBXjJDSd1OivRKEau1XXKU6w0ZV0wrKnYHRk5Bjpn0Oi3sMBxhaJ21ZOEUH04WDN3Ux6CsJJiXmSh6oIX2A X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(376002)(346002)(136003)(396003)(39860400002)(451199021)(40470700004)(36840700001)(46966006)(54906003)(316002)(478600001)(83380400001)(2616005)(336012)(426003)(6666004)(40480700001)(47076005)(36756003)(186003)(356005)(81166007)(82740400003)(36860700001)(82310400005)(26005)(7696005)(40460700003)(966005)(8936002)(70206006)(70586007)(41300700001)(6916009)(8676002)(2906002)(30864003)(4326008)(5660300002)(19627235002)(213903007)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 11:10:39.7577 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58ed4c8b-af28-46c2-ed74-08db39b437ee X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT067.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5036 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 Uses new SmmSmramSaveStateLib library. Removes old code. Cc: Paul Grimes Cc: Garrett Kirkendall Cc: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Gerd Hoffmann Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Signed-off-by: Abdul Lateef Attar --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 2 + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 2 + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 5 +- UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 500 +------------------ 4 files changed, 9 insertions(+), 500 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf b/UefiCpuPkg/PiSm= mCpuDxeSmm/PiSmmCpuDxeSmm.inf index 158e05e2646c..c57b6eea0e14 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf @@ -6,6 +6,7 @@ # # Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -97,6 +98,7 @@ [LibraryClasses] ReportStatusCodeLib SmmCpuFeaturesLib PeCoffGetEntryPointLib + SmmSmramSaveStateLib =20 [Protocols] gEfiSmmAccess2ProtocolGuid ## CONSUMES diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.h index a5c2bdd971ca..10df1e908ba8 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h @@ -3,6 +3,7 @@ Agent Module to load other modules to deploy SMM Entry Vect= or for X86 CPU. =20 Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -50,6 +51,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 #include #include diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index c0e368ea9475..64643aec54d0 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -3,6 +3,7 @@ Agent Module to load other modules to deploy SMM Entry Vect= or for X86 CPU. =20 Copyright (c) 2009 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -278,7 +279,7 @@ SmmReadSaveState ( =20 Status =3D SmmCpuFeaturesReadSaveStateRegister (CpuIndex, Register, Widt= h, Buffer); if (Status =3D=3D EFI_UNSUPPORTED) { - Status =3D ReadSaveStateRegister (CpuIndex, Register, Width, Buffer); + Status =3D SmramSaveStateReadRegister (CpuIndex, Register, Width, Buff= er); } =20 return Status; @@ -330,7 +331,7 @@ SmmWriteSaveState ( =20 Status =3D SmmCpuFeaturesWriteSaveStateRegister (CpuIndex, Register, Wid= th, Buffer); if (Status =3D=3D EFI_UNSUPPORTED) { - Status =3D WriteSaveStateRegister (CpuIndex, Register, Width, Buffer); + Status =3D SmramSaveStateWriteRegister (CpuIndex, Register, Width, Buf= fer); } =20 return Status; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmC= puDxeSmm/SmramSaveState.c index c8ddc6083df6..1e316ee0acdb 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c @@ -2,6 +2,8 @@ Provides services to access SMRAM Save State Map =20 Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -48,52 +50,6 @@ extern CONST PROCESSOR_SMM_DESCRIPTOR gcPsd; // #define LMA BIT10 =20 -/// -/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_S= TATE_LOOKUP_ENTRY -/// -#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field) - -/// -/// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_S= TATE_REGISTER_RANGE -/// -#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 } - -/// -/// Structure used to describe a range of registers -/// -typedef struct { - EFI_SMM_SAVE_STATE_REGISTER Start; - EFI_SMM_SAVE_STATE_REGISTER End; - UINTN Length; -} CPU_SMM_SAVE_STATE_REGISTER_RANGE; - -/// -/// Structure used to build a lookup table to retrieve the widths and offs= ets -/// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value -/// - -#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX 1 -#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX 2 -#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX 3 -#define SMM_SAVE_STATE_REGISTER_MAX_INDEX 4 - -typedef struct { - UINT8 Width32; - UINT8 Width64; - UINT16 Offset32; - UINT16 Offset64Lo; - UINT16 Offset64Hi; - BOOLEAN Writeable; -} CPU_SMM_SAVE_STATE_LOOKUP_ENTRY; - -/// -/// Structure used to build a lookup table for the IOMisc width informatio= n -/// -typedef struct { - UINT8 Width; - EFI_SMM_SAVE_STATE_IO_WIDTH IoWidth; -} CPU_SMM_SAVE_STATE_IO_WIDTH; - /// /// Variables from SMI Handler /// @@ -108,463 +64,11 @@ extern CONST UINT16 gcSmiHandlerSize; // IA32_DESCRIPTOR gSmiHandlerIdtr; =20 -/// -/// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGI= STER -/// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY -/// -CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] =3D { - SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_ST= ATE_REGISTER_LDTINFO), - SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_ST= ATE_REGISTER_RIP), - SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_ST= ATE_REGISTER_CR4), - { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_S= TATE_REGISTER)0, 0} -}; - -/// -/// Lookup table used to retrieve the widths and offsets associated with e= ach -/// supported EFI_SMM_SAVE_STATE_REGISTER value -/// -CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] =3D { - { 0, 0, 0, 0, = 0, FALSE }, // Reserved - - // - // Internally defined CPU Save State Registers. Not defined in PI SMM CP= U Protocol. - // - { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId), SMM_CPU_OFFSET (x64.SMMRevId), = 0, FALSE }, // SMM_SAVE_STATE_REGIST= ER_SMMREVID_INDEX =3D 1 - { 4, 4, SMM_CPU_OFFSET (x86.IOMisc), SMM_CPU_OFFSET (x64.IOMisc), = 0, FALSE }, // SMM_SAVE_STATE_REGIST= ER_IOMISC_INDEX =3D 2 - { 4, 8, SMM_CPU_OFFSET (x86.IOMemAddr), SMM_CPU_OFFSET (x64.IOMemAddr), = SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE }, // SMM_SAVE_STATE_REGIST= ER_IOMEMADDR_INDEX =3D 3 - - // - // CPU Save State registers defined in PI SMM CPU Protocol. - // - { 0, 8, 0, SMM_CPU_OFFSET (x64.GdtBaseLoDwo= rd), SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_GDTBASE =3D 4 - { 0, 8, 0, SMM_CPU_OFFSET (x64.IdtBaseLoDwo= rd), SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_IDTBASE =3D 5 - { 0, 8, 0, SMM_CPU_OFFSET (x64.LdtBaseLoDwo= rd), SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_LDTBASE =3D 6 - { 0, 0, 0, 0, = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_GDTLIMIT =3D 7 - { 0, 0, 0, 0, = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_IDTLIMIT =3D 8 - { 0, 0, 0, 0, = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_LDTLIMIT =3D 9 - { 0, 0, 0, 0, = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_LDTINFO =3D 10 - - { 4, 4, SMM_CPU_OFFSET (x86._ES), SMM_CPU_OFFSET (x64._ES), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_ES =3D 20 - { 4, 4, SMM_CPU_OFFSET (x86._CS), SMM_CPU_OFFSET (x64._CS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_CS =3D 21 - { 4, 4, SMM_CPU_OFFSET (x86._SS), SMM_CPU_OFFSET (x64._SS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_SS =3D 22 - { 4, 4, SMM_CPU_OFFSET (x86._DS), SMM_CPU_OFFSET (x64._DS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_DS =3D 23 - { 4, 4, SMM_CPU_OFFSET (x86._FS), SMM_CPU_OFFSET (x64._FS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_FS =3D 24 - { 4, 4, SMM_CPU_OFFSET (x86._GS), SMM_CPU_OFFSET (x64._GS), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_GS =3D 25 - { 0, 4, 0, SMM_CPU_OFFSET (x64._LDTR), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_LDTR_SEL =3D 26 - { 4, 4, SMM_CPU_OFFSET (x86._TR), SMM_CPU_OFFSET (x64._TR), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_TR_SEL =3D 27 - { 4, 8, SMM_CPU_OFFSET (x86._DR7), SMM_CPU_OFFSET (x64._DR7), = SMM_CPU_OFFSET (x64._DR7) + 4, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_DR7 =3D 28 - { 4, 8, SMM_CPU_OFFSET (x86._DR6), SMM_CPU_OFFSET (x64._DR6), = SMM_CPU_OFFSET (x64._DR6) + 4, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_DR6 =3D 29 - { 0, 8, 0, SMM_CPU_OFFSET (x64._R8), = SMM_CPU_OFFSET (x64._R8) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R8 =3D 30 - { 0, 8, 0, SMM_CPU_OFFSET (x64._R9), = SMM_CPU_OFFSET (x64._R9) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R9 =3D 31 - { 0, 8, 0, SMM_CPU_OFFSET (x64._R10), = SMM_CPU_OFFSET (x64._R10) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R10 =3D 32 - { 0, 8, 0, SMM_CPU_OFFSET (x64._R11), = SMM_CPU_OFFSET (x64._R11) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R11 =3D 33 - { 0, 8, 0, SMM_CPU_OFFSET (x64._R12), = SMM_CPU_OFFSET (x64._R12) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R12 =3D 34 - { 0, 8, 0, SMM_CPU_OFFSET (x64._R13), = SMM_CPU_OFFSET (x64._R13) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R13 =3D 35 - { 0, 8, 0, SMM_CPU_OFFSET (x64._R14), = SMM_CPU_OFFSET (x64._R14) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R14 =3D 36 - { 0, 8, 0, SMM_CPU_OFFSET (x64._R15), = SMM_CPU_OFFSET (x64._R15) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_R15 =3D 37 - { 4, 8, SMM_CPU_OFFSET (x86._EAX), SMM_CPU_OFFSET (x64._RAX), = SMM_CPU_OFFSET (x64._RAX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RAX =3D 38 - { 4, 8, SMM_CPU_OFFSET (x86._EBX), SMM_CPU_OFFSET (x64._RBX), = SMM_CPU_OFFSET (x64._RBX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RBX =3D 39 - { 4, 8, SMM_CPU_OFFSET (x86._ECX), SMM_CPU_OFFSET (x64._RCX), = SMM_CPU_OFFSET (x64._RCX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RCX =3D 40 - { 4, 8, SMM_CPU_OFFSET (x86._EDX), SMM_CPU_OFFSET (x64._RDX), = SMM_CPU_OFFSET (x64._RDX) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RDX =3D 41 - { 4, 8, SMM_CPU_OFFSET (x86._ESP), SMM_CPU_OFFSET (x64._RSP), = SMM_CPU_OFFSET (x64._RSP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RSP =3D 42 - { 4, 8, SMM_CPU_OFFSET (x86._EBP), SMM_CPU_OFFSET (x64._RBP), = SMM_CPU_OFFSET (x64._RBP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RBP =3D 43 - { 4, 8, SMM_CPU_OFFSET (x86._ESI), SMM_CPU_OFFSET (x64._RSI), = SMM_CPU_OFFSET (x64._RSI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RSI =3D 44 - { 4, 8, SMM_CPU_OFFSET (x86._EDI), SMM_CPU_OFFSET (x64._RDI), = SMM_CPU_OFFSET (x64._RDI) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RDI =3D 45 - { 4, 8, SMM_CPU_OFFSET (x86._EIP), SMM_CPU_OFFSET (x64._RIP), = SMM_CPU_OFFSET (x64._RIP) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RIP =3D 46 - - { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS), SMM_CPU_OFFSET (x64._RFLAGS), = SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE }, // EFI_SMM_SAVE_STATE_R= EGISTER_RFLAGS =3D 51 - { 4, 8, SMM_CPU_OFFSET (x86._CR0), SMM_CPU_OFFSET (x64._CR0), = SMM_CPU_OFFSET (x64._CR0) + 4, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_CR0 =3D 52 - { 4, 8, SMM_CPU_OFFSET (x86._CR3), SMM_CPU_OFFSET (x64._CR3), = SMM_CPU_OFFSET (x64._CR3) + 4, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_CR3 =3D 53 - { 0, 4, 0, SMM_CPU_OFFSET (x64._CR4), = 0, FALSE }, // EFI_SMM_SAVE_STATE_R= EGISTER_CR4 =3D 54 -}; - -/// -/// Lookup table for the IOMisc width information -/// -CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] =3D { - { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 0 - { 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // SMM_IO_LENGTH_BYTE =3D 1 - { 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 }, // SMM_IO_LENGTH_WORD =3D 2 - { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 3 - { 4, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 }, // SMM_IO_LENGTH_DWORD =3D 4 - { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 5 - { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }, // Undefined =3D 6 - { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 } // Undefined =3D 7 -}; - -/// -/// Lookup table for the IOMisc type information -/// -CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] =3D { - EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_DX =3D = 0 - EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_IN_DX =3D = 1 - EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_OUTS =3D = 2 - EFI_SMM_SAVE_STATE_IO_TYPE_STRING, // SMM_IO_TYPE_INS =3D = 3 - (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 4 - (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 5 - EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_OUTS =3D = 6 - EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX, // SMM_IO_TYPE_REP_INS =3D = 7 - EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT, // SMM_IO_TYPE_OUT_IMMEDIATE =3D = 8 - EFI_SMM_SAVE_STATE_IO_TYPE_INPUT, // SMM_IO_TYPE_OUT_IMMEDIATE =3D = 9 - (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 10 - (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 11 - (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 12 - (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 13 - (EFI_SMM_SAVE_STATE_IO_TYPE)0, // Undefined =3D = 14 - (EFI_SMM_SAVE_STATE_IO_TYPE)0 // Undefined =3D = 15 -}; - /// /// The mode of the CPU at the time an SMI occurs /// UINT8 mSmmSaveStateRegisterLma; =20 -/** - Read information from the CPU save state. - - @param Register Specifies the CPU register to read form the save state= . - - @retval 0 Register is not valid - @retval >0 Index into mSmmCpuWidthOffset[] associated with Register - -**/ -UINTN -GetRegisterIndex ( - IN EFI_SMM_SAVE_STATE_REGISTER Register - ) -{ - UINTN Index; - UINTN Offset; - - for (Index =3D 0, Offset =3D SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuR= egisterRanges[Index].Length !=3D 0; Index++) { - if ((Register >=3D mSmmCpuRegisterRanges[Index].Start) && (Register <= =3D mSmmCpuRegisterRanges[Index].End)) { - return Register - mSmmCpuRegisterRanges[Index].Start + Offset; - } - - Offset +=3D mSmmCpuRegisterRanges[Index].Length; - } - - return 0; -} - -/** - Read a CPU Save State register on the target processor. - - This function abstracts the differences that whether the CPU Save State = register is in the - IA32 CPU Save State Map or X64 CPU Save State Map. - - This function supports reading a CPU Save State register in SMBase reloc= ation handler. - - @param[in] CpuIndex Specifies the zero-based index of the CPU sav= e state. - @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table= . - @param[in] Width The number of bytes to read from the CPU save= state. - @param[out] Buffer Upon return, this holds the CPU register valu= e read from the save state. - - @retval EFI_SUCCESS The register was read from Save State. - @retval EFI_NOT_FOUND The register is not defined for the Save S= tate of Processor. - @retval EFI_INVALID_PARAMETER This or Buffer is NULL. - -**/ -EFI_STATUS -ReadSaveStateRegisterByIndex ( - IN UINTN CpuIndex, - IN UINTN RegisterIndex, - IN UINTN Width, - OUT VOID *Buffer - ) -{ - SMRAM_SAVE_STATE_MAP *CpuSaveState; - - if (RegisterIndex =3D=3D 0) { - return EFI_NOT_FOUND; - } - - CpuSaveState =3D gSmst->CpuSaveState[CpuIndex]; - - if (mSmmSaveStateRegisterLma =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BI= T) { - // - // If 32-bit mode width is zero, then the specified register can not b= e accessed - // - if (mSmmCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { - return EFI_NOT_FOUND; - } - - // - // If Width is bigger than the 32-bit mode width, then the specified r= egister can not be accessed - // - if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) { - return EFI_INVALID_PARAMETER; - } - - // - // Write return buffer - // - ASSERT (CpuSaveState !=3D NULL); - CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIn= dex].Offset32, Width); - } else { - // - // If 64-bit mode width is zero, then the specified register can not b= e accessed - // - if (mSmmCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { - return EFI_NOT_FOUND; - } - - // - // If Width is bigger than the 64-bit mode width, then the specified r= egister can not be accessed - // - if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) { - return EFI_INVALID_PARAMETER; - } - - // - // Write at most 4 of the lower bytes of the return buffer - // - CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIn= dex].Offset64Lo, MIN (4, Width)); - if (Width > 4) { - // - // Write at most 4 of the upper bytes of the return buffer - // - CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOf= fset[RegisterIndex].Offset64Hi, Width - 4); - } - } - - return EFI_SUCCESS; -} - -/** - Read a CPU Save State register on the target processor. - - This function abstracts the differences that whether the CPU Save State = register is in the - IA32 CPU Save State Map or X64 CPU Save State Map. - - This function supports reading a CPU Save State register in SMBase reloc= ation handler. - - @param[in] CpuIndex Specifies the zero-based index of the CPU sav= e state. - @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table= . - @param[in] Width The number of bytes to read from the CPU save= state. - @param[out] Buffer Upon return, this holds the CPU register valu= e read from the save state. - - @retval EFI_SUCCESS The register was read from Save State. - @retval EFI_NOT_FOUND The register is not defined for the Save S= tate of Processor. - @retval EFI_INVALID_PARAMETER Buffer is NULL, or Width does not meet req= uirement per Register type. - -**/ -EFI_STATUS -EFIAPI -ReadSaveStateRegister ( - IN UINTN CpuIndex, - IN EFI_SMM_SAVE_STATE_REGISTER Register, - IN UINTN Width, - OUT VOID *Buffer - ) -{ - UINT32 SmmRevId; - SMRAM_SAVE_STATE_IOMISC IoMisc; - EFI_SMM_SAVE_STATE_IO_INFO *IoInfo; - - // - // Check for special EFI_SMM_SAVE_STATE_REGISTER_LMA - // - if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA) { - // - // Only byte access is supported for this register - // - if (Width !=3D 1) { - return EFI_INVALID_PARAMETER; - } - - *(UINT8 *)Buffer =3D mSmmSaveStateRegisterLma; - - return EFI_SUCCESS; - } - - // - // Check for special EFI_SMM_SAVE_STATE_REGISTER_IO - // - if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_IO) { - // - // Get SMM Revision ID - // - ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREV= ID_INDEX, sizeof (SmmRevId), &SmmRevId); - - // - // See if the CPU supports the IOMisc register in the save state - // - if (SmmRevId < SMRAM_SAVE_STATE_MIN_REV_ID_IOMISC) { - return EFI_NOT_FOUND; - } - - // - // Get the IOMisc register value - // - ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC= _INDEX, sizeof (IoMisc.Uint32), &IoMisc.Uint32); - - // - // Check for the SMI_FLAG in IOMisc - // - if (IoMisc.Bits.SmiFlag =3D=3D 0) { - return EFI_NOT_FOUND; - } - - // - // Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS. - // - if ((mSmmCpuIoType[IoMisc.Bits.Type] !=3D EFI_SMM_SAVE_STATE_IO_TYPE_I= NPUT) && - (mSmmCpuIoType[IoMisc.Bits.Type] !=3D EFI_SMM_SAVE_STATE_IO_TYPE_O= UTPUT)) - { - return EFI_NOT_FOUND; - } - - // - // Compute index for the I/O Length and I/O Type lookup tables - // - if ((mSmmCpuIoWidth[IoMisc.Bits.Length].Width =3D=3D 0) || (mSmmCpuIoT= ype[IoMisc.Bits.Type] =3D=3D 0)) { - return EFI_NOT_FOUND; - } - - // - // Make sure the incoming buffer is large enough to hold IoInfo before= accessing - // - if (Width < sizeof (EFI_SMM_SAVE_STATE_IO_INFO)) { - return EFI_INVALID_PARAMETER; - } - - // - // Zero the IoInfo structure that will be returned in Buffer - // - IoInfo =3D (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer; - ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO)); - - // - // Use lookup tables to help fill in all the fields of the IoInfo stru= cture - // - IoInfo->IoPort =3D (UINT16)IoMisc.Bits.Port; - IoInfo->IoWidth =3D mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth; - IoInfo->IoType =3D mSmmCpuIoType[IoMisc.Bits.Type]; - ReadSaveStateRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX, mSmm= CpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData); - return EFI_SUCCESS; - } - - // - // Convert Register to a register lookup table index - // - return ReadSaveStateRegisterByIndex (CpuIndex, GetRegisterIndex (Registe= r), Width, Buffer); -} - -/** - Write value to a CPU Save State register on the target processor. - - This function abstracts the differences that whether the CPU Save State = register is in the - IA32 CPU Save State Map or X64 CPU Save State Map. - - This function supports writing a CPU Save State register in SMBase reloc= ation handler. - - @param[in] CpuIndex Specifies the zero-based index of the CPU save= state. - @param[in] RegisterIndex Index into mSmmCpuWidthOffset[] look up table. - @param[in] Width The number of bytes to read from the CPU save = state. - @param[in] Buffer Upon entry, this holds the new CPU register va= lue. - - @retval EFI_SUCCESS The register was written to Save State. - @retval EFI_NOT_FOUND The register is not defined for the Save S= tate of Processor. - @retval EFI_INVALID_PARAMETER ProcessorIndex or Width is not correct. - -**/ -EFI_STATUS -EFIAPI -WriteSaveStateRegister ( - IN UINTN CpuIndex, - IN EFI_SMM_SAVE_STATE_REGISTER Register, - IN UINTN Width, - IN CONST VOID *Buffer - ) -{ - UINTN RegisterIndex; - SMRAM_SAVE_STATE_MAP *CpuSaveState; - - // - // Writes to EFI_SMM_SAVE_STATE_REGISTER_LMA are ignored - // - if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA) { - return EFI_SUCCESS; - } - - // - // Writes to EFI_SMM_SAVE_STATE_REGISTER_IO are not supported - // - if (Register =3D=3D EFI_SMM_SAVE_STATE_REGISTER_IO) { - return EFI_NOT_FOUND; - } - - // - // Convert Register to a register lookup table index - // - RegisterIndex =3D GetRegisterIndex (Register); - if (RegisterIndex =3D=3D 0) { - return EFI_NOT_FOUND; - } - - CpuSaveState =3D gSmst->CpuSaveState[CpuIndex]; - - // - // Do not write non-writable SaveState, because it will cause exception. - // - if (!mSmmCpuWidthOffset[RegisterIndex].Writeable) { - return EFI_UNSUPPORTED; - } - - // - // Check CPU mode - // - if (mSmmSaveStateRegisterLma =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BI= T) { - // - // If 32-bit mode width is zero, then the specified register can not b= e accessed - // - if (mSmmCpuWidthOffset[RegisterIndex].Width32 =3D=3D 0) { - return EFI_NOT_FOUND; - } - - // - // If Width is bigger than the 32-bit mode width, then the specified r= egister can not be accessed - // - if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) { - return EFI_INVALID_PARAMETER; - } - - // - // Write SMM State register - // - ASSERT (CpuSaveState !=3D NULL); - CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Off= set32, Buffer, Width); - } else { - // - // If 64-bit mode width is zero, then the specified register can not b= e accessed - // - if (mSmmCpuWidthOffset[RegisterIndex].Width64 =3D=3D 0) { - return EFI_NOT_FOUND; - } - - // - // If Width is bigger than the 64-bit mode width, then the specified r= egister can not be accessed - // - if (Width > mSmmCpuWidthOffset[RegisterIndex].Width64) { - return EFI_INVALID_PARAMETER; - } - - // - // Write at most 4 of the lower bytes of SMM State register - // - CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Off= set64Lo, Buffer, MIN (4, Width)); - if (Width > 4) { - // - // Write at most 4 of the upper bytes of SMM State register - // - CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].O= ffset64Hi, (UINT8 *)Buffer + 4, Width - 4); - } - } - - return EFI_SUCCESS; -} - /** Hook the code executed immediately after an RSM instruction on the curre= ntly executing CPU. The mode of code executed immediately after RSM must be --=20 2.25.1