Re: [edk2-devel] [edk2-platforms PATCH 12/19] AmpereAltraPkg/Ac01PcieLib: fix compilation error

["Nhi Pham via groups.io" <nhi=os.amperecomputing.com@groups.io>]

Thanks for fixing it.

Reviewed-by: Nhi Pham <nhi@os.amperecomputing.com>

Regards,
Nhi

On 10/12/2023 4:09 PM, Laszlo Ersek wrote:
> Commit 380b4b40c60d ("AmpereAltraPkg: Update Ampere specific platform PCIe
> core", 2023-03-29) removed the DEBUG macro call from
> Ac01PcieCoreUpdateLink() that was the only reader of "Val". Since then,
> Val has only been set, but never read. This triggers
> "-Werror=unused-but-set-variable".
> 
> Found when trying to build "Jade.dsc".
> 
> Keep the MmioRead32() call, so that the PCIe config space sees the same
> behavior as before, but explicitly throw away the result.
> 
> Cc: Chuong Tran <chuong@os.amperecomputing.com>
> Cc: Leif Lindholm <quic_llindhol@quicinc.com>
> Cc: Nhi Pham <nhi@os.amperecomputing.com>
> Cc: Rebecca Cran <rebecca@os.amperecomputing.com>
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=4564
> Signed-off-by: Laszlo Ersek <lersek@redhat.com>
> ---
>   Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c
> index 3c1fe5e35ca2..fa00c1e36999 100644
> --- a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c
> +++ b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c
> @@ -1747,7 +1747,6 @@ Ac01PcieCoreUpdateLink (
>     PHYSICAL_ADDRESS          CfgBase;
>     UINT8                     PcieIndex;
>     UINT32                    Index;
> -  UINT32                    Val;
>   
>     *IsNextRoundNeeded = FALSE;
>     *FailedPcieCount   = 0;
> @@ -1767,7 +1766,7 @@ Ac01PcieCoreUpdateLink (
>       if (Pcie->Active && !Pcie->LinkUp) {
>         if (PcieLinkUpCheck (Pcie)) {
>           Pcie->LinkUp = TRUE;
> -        Val = MmioRead32 (CfgBase + PCIE_CAPABILITY_BASE + LINK_CONTROL_LINK_STATUS_REG);
> +        (VOID)MmioRead32 (CfgBase + PCIE_CAPABILITY_BASE + LINK_CONTROL_LINK_STATUS_REG);
>   
>           // Doing link checking and recovery if needed
>           Ac01PcieCoreQoSLinkCheckRecovery (RootComplex, PcieIndex);
> 


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