Re: [edk2-devel] [PATCH 1/1] MdePkg/BaseLib: Add SpeculationBarrier implementation for RiscV64

["Li, Yong" <yong.li@intel.com>]

On 2023/6/1 15:26, Sunil V L wrote:
> On Mon, May 29, 2023 at 01:51:46PM +0800, Li, Yong wrote:
>>
>> Hi Sunil,
>>
>> Could you help review this my first patch to edk2 community for RiscV,  this is the change to MdePkg/Library/BaseLib/RiscV64. 
>> Since it is for RiscV specific, I guess you are the only maintainer per the Maintainers.txt  ?
>> Please let me know if need additional reviewer.  
>>
>> Thanks in advance for your time and kind helping for this first patch.
>>
> Hi Yong,
> 
> Thank you for the patch!
> 
> Just one typo in the commit text and one question below. Otherwise, LGTM.
> 
>>
>> On 2023/5/29 13:24, Li, Yong wrote:
>>> Impelement the SpeculationBarrier with implementations consisting of
> 
> typo - "Implement"
> 

Hi Sunil,

Thanks for the careful review, Let me change in v2


>>> fence instruction which provides finer-grain memory orderings.
>>> Perform Data Barrier in RiscV: fence rw,rw
>>> Perform Instruction Barrier in RiscV: fence.i; fence r,r
>>> More detail is in Chapter 17, RVWMO Memory Consistency Model
>>> https://github.com/riscv/riscv-isa-manual
>>>
>>> This API is first introduced in the below commits for IA32 and x64
>>> https://github.com/tianocore/edk2/commit/d9f1cac51bd354507e880e614d11a1dc160d38a3
>>> https://github.com/tianocore/edk2/commit/e83d841fdc2878959185c4c6cc38a7a1e88377a4
>>> and below the commit for ARM and AArch64 implementation
>>> https://github.com/tianocore/edk2/commit/c0959b4426b2da45cdb8146a5116bb4fd9b86534
>>>
>>> This commit is to add the RiscV64 implementation which will be used by
>>> variable service under Variable/RuntimeDxe
>>>
>>> Cc: Andrei Warkentin <andrei.warkentin@intel.com>
>>> Cc: Evan Chai <evan.chai@intel.com>
>>> Cc: Sunil V L <sunilvl@ventanamicro.com>
>>> Cc: Tuan Phan <tphan@ventanamicro.com>
>>> Signed-off-by: Yong Li <yong.li@intel.com>
>>> ---
>>>  MdePkg/Library/BaseLib/BaseLib.inf            |  1 +
>>>  .../BaseLib/RiscV64/SpeculationBarrier.S      | 34 +++++++++++++++++++
>>>  2 files changed, 35 insertions(+)
>>>  create mode 100644 MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S
>>>
>>> diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
>>> index 3a48492b1a01..03c7b02e828b 100644
>>> --- a/MdePkg/Library/BaseLib/BaseLib.inf
>>> +++ b/MdePkg/Library/BaseLib/BaseLib.inf
>>> @@ -404,6 +404,7 @@ [Sources.RISCV64]
>>>    RiscV64/CpuScratch.S              | GCC
>>>    RiscV64/ReadTimer.S               | GCC
>>>    RiscV64/RiscVMmu.S                | GCC
>>> +  RiscV64/SpeculationBarrier.S      | GCC
>>>  
>>>  [Sources.LOONGARCH64]
>>>    Math64.c
>>> diff --git a/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S b/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S
>>> new file mode 100644
>>> index 000000000000..581a7653996f
>>> --- /dev/null
>>> +++ b/MdePkg/Library/BaseLib/RiscV64/SpeculationBarrier.S
>>> @@ -0,0 +1,34 @@
>>> +##------------------------------------------------------------------------------
>>> +#
>>> +# SpeculationBarrier() for RISCV64
>>> +#
>>> +# Copyright (c) 2023, Intel Corporation. All rights reserved.
>>> +#
>>> +# SPDX-License-Identifier: BSD-2-Clause-Patent
>>> +#
>>> +##------------------------------------------------------------------------------
>>> +
>>> +.text
>>> +.p2align 2
>>> +
>>> +ASM_GLOBAL ASM_PFX(SpeculationBarrier)
>>> +
>>> +
>>> +#/**
>>> +#  Uses as a barrier to stop speculative execution.
>>> +#
>>> +#  Ensures that no later instruction will execute speculatively, until all prior
>>> +#  instructions have completed.
>>> +#
>>> +#**/
>>> +#VOID
>>> +#EFIAPI
>>> +#SpeculationBarrier (
>>> +#  VOID
>>> +#  );
>>> +#
>>> +ASM_PFX(SpeculationBarrier):
>>> +    fence rw,rw
> 
> Don't we need fence iorw, iorw?
> 

This SpeculationBarrier function is to avoid the speculative execution for the potential risk introduced in branch prediction mentioned in https://nvd.nist.gov/vuln/detail/cve-2017-5753.
Thus, I think no need to enforce ordering on devices, just memory, data barrier and instruction barrier.
Also in ARM's implementation MdePkg/Library/BaseLib/AArch64/SpeculationBarrier.S, similar dsb and isb instructions are used, 
one for data barrier and another for instruction barrier. 

And from the RISC-V spec https://github.com/riscv/riscv-isa-manual/blob/main/src/mm-eplan.adoc,
the data barrier and instruction barrier RVWMO mapping are
Power Operation 	RVWMO Mapping
sync			fence rw,rw
isync                   fence.i; fence r,r


> Thanks,
> Sunil
> 
>>> +    fence.i
>>> +    fence r,r
>>> +    ret
> 
> 
> 
> 
> 
>