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[88.152.145.137]) by smtp.gmail.com with ESMTPSA id n12-20020a05600c294c00b003dc42d48defsm4446354wmd.6.2023.02.17.02.12.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Feb 2023 02:12:25 -0800 (PST) Message-ID: <0d898a1b-a5ee-a037-c7da-4a12c170aad9@canonical.com> Date: Fri, 17 Feb 2023 11:12:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.2 Subject: Re: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V8 00/19] Add support for RISC-V virt machine To: Michael Brown Cc: Abner Chang , Daniel Schaefer , Michael D Kinney , Liming Gao , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Sami Mujawar , Leif Lindholm , Eric Dong , Ray Ni , Rahul Kumar , Zhiguang Liu , Anup Patel , Andrei Warkentin , devel@edk2.groups.io, sunilvl@ventanamicro.com, dann frazier References: <20230210123041.1489506-1-sunilvl@ventanamicro.com> <010201865ea973b9-f0358277-9198-4adc-a8c9-9c106220b25a-000000@eu-west-1.amazonses.com> From: Heinrich Schuchardt In-Reply-To: <010201865ea973b9-f0358277-9198-4adc-a8c9-9c106220b25a-000000@eu-west-1.amazonses.com> Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable On 2/17/23 10:16, Michael Brown wrote: > On 17/02/2023 04:27, Sunil V L wrote: >> On Thu, Feb 16, 2023 at 03:45:49PM -0700, dann frazier wrote: >>> =C2=A0=C2=A0 Thanks for your work getting this merged! In the above w= iki, it >>> notes that GCC 12+ is not supported. Is that still accurate? If so, >>> can you clarify what is blocking that? >> >> Please see https://bugzilla.tianocore.org/show_bug.cgi?id=3D4061. >> >> My attempt to fix this issue >> (https://edk2.groups.io/g/devel/message/93831) was not accepted due to >> the concerns that it can cause weird issues in CI. >> >> So, we are left with either support gcc <12 or gcc >=3D12. We can mand= ate >> gcc 12 itself for RISC-V, but that change need to be done hand in hand >> with CI tests moving to use gcc 12. Otherwise, it will break CI. >=20 > Is there an alternative (and presumably less ideal) way to force an=20 > instruction cache invalidation?=C2=A0 For example, does a global TSO "f= ence"=20 > instruction as used in RiscVInvalidateDataCacheAsm() also invalidate th= e=20 > instruction cache? >=20 > If so, then a viable solution would be: >=20 > --- a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S > +++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S > @@ -15,3 +15,7 @@ ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm) > =C2=A0ASM_PFX(RiscVInvalidateInstCacheAsm): > -=C2=A0=C2=A0=C2=A0 fence.i > +#ifdef __riscv_zifencei > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 fence.i > +#else > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 fence > +#endif > =C2=A0=C2=A0=C2=A0=C2=A0 ret >=20 >=20 > This would also permit EDK2 to be used on implementations that genuinel= y=20 > do not provide the fence.i instruction. >=20 > Michael >=20 fence.i is the right instruction to use. The problem are not platforms=20 that do not provide the fence.i instruction but that the fence.i=20 instruction was removed from RVGC64 in the specification. Now all programs like OpenSBI, U-Boot, Linux have to be compiled with=20 different -march parameters for GCC11 and GCC12. Sunil suggested dropping support for GCC < 12. This seems to be the=20 easiest approach. An alternative would be adding a GCC12 profile to=20 BaseTools/Conf/tools_def.template but that would create a high effort. Best regards Heinrich