From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by mx.groups.io with SMTP id smtpd.web09.4070.1662524732619877926 for ; Tue, 06 Sep 2022 21:25:32 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Zh/ckObF; spf=permerror, err=parse error for token &{10 18 %{ir}.%{v}.%{d}.spf.has.pphosted.com}: invalid domain name (domain: quicinc.com, ip: 205.220.180.131, mailfrom: quic_rcran@quicinc.com) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2874E2nZ025927; Wed, 7 Sep 2022 04:25:22 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=U/62RxG8O/XQOflH9BJplTkFHsGzyulXu9MtuvjW+yU=; b=Zh/ckObFmyzqewvv5AJ/iVBn+zyI8h4yUTBow1jqb7PXjMNwL+K8ppz4hfwuFZzNpiaN wCeyHGvI1CvVAUsfBjC8zaXw1ZTds0Dn1gF0BmDF3hShbFngL/2gVnSeSjSiKm9RD/Ou cdeHHDxahIaeVBDd2fF0b7TIle++q+681JHEp8Qd611mxkk/LcTH8Uyq+Tqrlua7XTgf 8+IP2FoGiyzgs/uFyLeLVcwKb7KsP3gunbnv9ErcsfSED/vIn/f4Yi1l9vZBCwA3X6SO pwqlhODxNd6ccEwxjIhQ5MiCI/IH1FV/kHw0Ynvf5HBcx87RDF9Z2JMPT1diTHuXUDgX 6g== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jefarrjcn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 07 Sep 2022 04:25:21 +0000 Received: from nasanex01b.na.qualcomm.com (corens_vlan604_snip.qualcomm.com [10.53.140.1]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 2874PKMY024747 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 7 Sep 2022 04:25:20 GMT Received: from [10.110.11.216] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 6 Sep 2022 21:25:20 -0700 Message-ID: <0d995c50-4964-2937-1e2e-c4fbb9fce584@quicinc.com> Date: Tue, 6 Sep 2022 22:25:19 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.1 Subject: Re: [PATCH v2 1/2] ArmPkg: implement EFI_MP_SERVICES_PROTOCOL based on PSCI calls To: , , , Sami Mujawar , Jian J Wang , Liming Gao References: <20220907040326.388003-1-rebecca@quicinc.com> <20220907040326.388003-2-rebecca@quicinc.com> From: "Rebecca Cran" In-Reply-To: <20220907040326.388003-2-rebecca@quicinc.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WmWyGNm_lQmNiueGysnp7NLWpIcUPRPJ X-Proofpoint-ORIG-GUID: WmWyGNm_lQmNiueGysnp7NLWpIcUPRPJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-09-07_02,2022-09-06_02,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 impostorscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 mlxlogscore=969 adultscore=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2209070016 Content-Language: en-US Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit On 9/6/22 22:03, Rebecca Cran wrote: > diff --git a/ArmPkg/ArmPkg.dsc b/ArmPkg/ArmPkg.dsc > index 59fd8f295d4f..4716789402fc 100644 > --- a/ArmPkg/ArmPkg.dsc > +++ b/ArmPkg/ArmPkg.dsc > @@ -125,6 +125,7 @@ [Components.common] > ArmPkg/Drivers/CpuPei/CpuPei.inf > ArmPkg/Drivers/ArmGic/ArmGicDxe.inf > ArmPkg/Drivers/ArmGic/ArmGicLib.inf > + ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.inf > ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf > ArmPkg/Drivers/TimerDxe/TimerDxe.inf This won't work, since there's no support for 32-bit ARM code. I'll move it into the AARCH64 section. -- Rebecca Cran