From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=209.132.183.28; helo=mx1.redhat.com; envelope-from=lersek@redhat.com; receiver=edk2-devel@lists.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 61E3821A02937 for ; Wed, 28 Nov 2018 10:45:03 -0800 (PST) Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id DEE2530832EA; Wed, 28 Nov 2018 18:45:02 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-170.rdu2.redhat.com [10.10.120.170]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9C0D760123; Wed, 28 Nov 2018 18:44:56 +0000 (UTC) To: Ard Biesheuvel , edk2-devel@lists.01.org Cc: Leif Lindholm , Eric Auger , Andrew Jones , Philippe Mathieu-Daude , Julien Grall References: <20181128143357.991-1-ard.biesheuvel@linaro.org> <20181128143357.991-7-ard.biesheuvel@linaro.org> From: Laszlo Ersek Message-ID: <0e6834ff-5ecf-7a32-99ad-28e4a2ed0c23@redhat.com> Date: Wed, 28 Nov 2018 19:44:55 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20181128143357.991-7-ard.biesheuvel@linaro.org> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.44]); Wed, 28 Nov 2018 18:45:03 +0000 (UTC) Subject: Re: [PATCH v3 06/16] ArmPkg/ArmLib: add support for reading the max physical address space size X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Nov 2018 18:45:03 -0000 Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 11/28/18 15:33, Ard Biesheuvel wrote: > Add a helper function that returns the maximum physical address space > size as supported by the current CPU. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Include/Library/ArmLib.h | 6 ++++++ > ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 17 +++++++++++++++++ > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 8 ++++++++ > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm | 8 ++++++++ > 4 files changed, 39 insertions(+) > > diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h > index ffda50e9d767..9a804c15fdb6 100644 > --- a/ArmPkg/Include/Library/ArmLib.h > +++ b/ArmPkg/Include/Library/ArmLib.h > @@ -733,4 +733,10 @@ ArmWriteCntvOff ( > UINT64 Val > ); > > +UINTN > +EFIAPI > +ArmGetPhysicalAddressBits ( > + VOID > + ); > + > #endif // __ARM_LIB__ > diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > index 1ef2f61f5979..b7173e00b039 100644 > --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S > @@ -196,4 +196,21 @@ ASM_FUNC(ArmWriteSctlr) > 3:msr sctlr_el3, x0 > 4:ret > > +ASM_FUNC(ArmGetPhysicalAddressBits) > + mrs x0, id_aa64mmfr0_el1 > + adr x1, .LPARanges > + and x0, x0, #0xf > + ldrb w0, [x1, x0] > + ret > + > +// > +// Bits 0..3 of the AA64MFR0_EL1 system register encode the size of the > +// physical address space support on this CPU: > +// 0 == 32 bits, 1 == 36 bits, etc etc > +// 7 and up are reserved > +// > +.LPARanges: > + .byte 32, 36, 40, 42, 44, 48, 52, 0 > + .byte 0, 0, 0, 0, 0, 0, 0, 0 > + > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > index f2a517671f0a..0e9f9d0453e4 100644 > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > @@ -165,4 +165,12 @@ ASM_FUNC(ArmWriteCpuActlr) > isb > bx lr > > +ASM_FUNC (ArmGetPhysicalAddressBits) > + mrc p15, 0, r0, c0, c1, 4 // MMFR0 > + and r0, r0, #0xf // VMSA [3:0] > + cmp r0, #5 // >= 5 implies LPAE support > + movlt r0, #32 // 32 bits if no LPAE > + movge r0, #40 // 40 bits if LPAE > + bx lr > + > ASM_FUNCTION_REMOVE_IF_UNREFERENCED > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm > index 219140c22b13..3eb52875971d 100644 > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.asm > @@ -169,4 +169,12 @@ > isb > bx lr > > + RVCT_ASM_EXPORT ArmGetPhysicalAddressBits > + mrc p15, 0, r0, c0, c1, 4 ; MMFR0 > + and r0, r0, #0xf ; VMSA [3:0] > + cmp r0, #5 ; >= 5 implies LPAE support > + movlt r0, #32 ; 32 bits if no LPAE > + movge r0, #40 ; 40 bits if LPAE > + bx lr > + > END > I didn't review the assembly code, but formally, the patch looks OK to me. Acked-by: Laszlo Ersek