From: "Benjamin Doron" <benjamin.doron00@gmail.com>
To: devel@edk2.groups.io
Cc: Chasel Chiu <chasel.chiu@intel.com>,
Nate DeSimone <nathaniel.l.desimone@intel.com>,
Ankit Sinha <ankit.sinha@intel.com>,
Isaac Oram <isaac.w.oram@intel.com>,
Liming Gao <gaoliming@byosoft.com.cn>,
Eric Dong <eric.dong@intel.com>
Subject: [edk2-devel][edk2-platforms][PATCH v2 5/6] MinPlatformPkg: Implement working S3 resume
Date: Tue, 6 Sep 2022 13:02:27 -0400 [thread overview]
Message-ID: <0e97006ee5e35e8399bd8fe1b463664c301c5644.1662483691.git.benjamin.doron00@gmail.com> (raw)
In-Reply-To: <cover.1662483691.git.benjamin.doron00@gmail.com>
Consume S3 resume memory allocation on resume flow.
Also, include complementary FirmwarePerformanceDataTablePei module in
MinPlatform FV for S3 resume performance measurement.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../FspWrapperHobProcessLib.c | 69 ++++++++++++++++++-
.../PeiFspWrapperHobProcessLib.inf | 2 +
.../Include/Dsc/CorePeiInclude.dsc | 2 +
.../Include/Fdf/CorePostMemoryInclude.fdf | 2 +
4 files changed, 74 insertions(+), 1 deletion(-)
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
index 7ee4d3a31c49..9bd6fe6290c5 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
@@ -16,14 +16,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/FspWrapperPlatformLib.h>
+#include <Guid/AcpiS3Context.h>
#include <Guid/GuidHobFspEas.h>
#include <Guid/MemoryTypeInformation.h>
#include <Guid/GraphicsInfoHob.h>
#include <Guid/PcdDataBaseHobGuid.h>
#include <Guid/ZeroGuid.h>
#include <Ppi/Capsule.h>
+#include <Ppi/ReadOnlyVariable2.h>
#include <FspEas.h>
+#include <AcpiS3MemoryNvData.h>
//
// Additional pages are used by DXE memory manager.
@@ -130,6 +133,55 @@ GetPeiMemSize (
return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE;
}
+/**
+ Get S3 PEI memory information.
+
+ @note At this point, memory is ready, and PeiServices are available to use.
+ Platform can get some data from SMRAM directly.
+
+ @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.
+ @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.
+
+ @return If S3 PEI memory information is got successfully.
+**/
+EFI_STATUS
+EFIAPI
+GetS3MemoryInfo (
+ OUT UINT64 *S3PeiMemSize,
+ OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
+ UINTN DataSize;
+ ACPI_S3_MEMORY S3MemoryInfo;
+
+ *S3PeiMemBase = 0;
+ *S3PeiMemSize = 0;
+
+ Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, (VOID **) &VariablePpi);
+ ASSERT_EFI_ERROR (Status);
+
+ DataSize = sizeof (S3MemoryInfo);
+ Status = VariablePpi->GetVariable (
+ VariablePpi,
+ ACPI_S3_MEMORY_NV_NAME,
+ &gEfiAcpiVariableGuid,
+ NULL,
+ &DataSize,
+ &S3MemoryInfo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *S3PeiMemBase = S3MemoryInfo.S3PeiMemBase;
+ *S3PeiMemSize = S3MemoryInfo.S3PeiMemSize;
+ return EFI_SUCCESS;
+}
+
/**
Post FSP-M HOB process for Memory Resource Descriptor.
@@ -280,7 +332,7 @@ PostFspmHobProcess (
0x1000
);
-
+ if (BootMode != BOOT_ON_S3_RESUME) {
//
// Capsule mode
//
@@ -337,7 +389,22 @@ PostFspmHobProcess (
if (Capsule != NULL) {
Status = Capsule->CreateState ((EFI_PEI_SERVICES **)PeiServices, CapsuleBuffer, CapsuleBufferLength);
}
+ } else {
+ Status = GetS3MemoryInfo (&PeiMemSize, &PeiMemBase);
+ ASSERT_EFI_ERROR (Status);
+ DEBUG ((DEBUG_INFO, "S3 resume PeiMemBase : 0x%08x\n", PeiMemBase));
+ DEBUG ((DEBUG_INFO, "S3 resume PeiMemSize : 0x%08x\n", PeiMemSize));
+
+ //
+ // Install efi memory
+ //
+ Status = PeiServicesInstallPeiMemory (
+ PeiMemBase,
+ PeiMemSize
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
//
// Create a memory allocation HOB at fixed location for MP Services PPI AP wait loop.
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
index b846e7af1d2d..e2aac36bf018 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
@@ -75,7 +75,9 @@
gZeroGuid
gEfiGraphicsInfoHobGuid
gEfiGraphicsDeviceInfoHobGuid
+ gEfiAcpiVariableGuid
[Ppis]
gEfiPeiCapsulePpiGuid ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
gEdkiiSiliconInitializedPpiGuid ## PRODUCES
diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
index 08e50cac075f..f271fb26b189 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
+++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
@@ -41,3 +41,5 @@
NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf
}
!endif
+
+ MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
index 3c2716d6728a..160f02650a8c 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
+++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
@@ -6,3 +6,5 @@
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
+
+ INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
--
2.37.2
next prev parent reply other threads:[~2022-09-06 17:02 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-06 17:02 [edk2-devel][edk2-platforms][PATCH v2 0/6] Implement S3 resume Benjamin Doron
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 1/6] {Platform,Silicon}/Intel: Move PcdAcpiBaseAddress definition Benjamin Doron
2022-09-07 22:50 ` Isaac Oram
2022-09-07 22:57 ` Chaganty, Rangasai V
2022-09-09 21:11 ` Isaac Oram
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 2/6] IntelSiliconPkg/Feature/SmmAccess: Implement PPI with chipset support Benjamin Doron
2022-09-07 23:49 ` Isaac Oram
[not found] ` <1712B8F6079EA3A9.20240@groups.io>
2022-09-09 21:13 ` Isaac Oram
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: " Benjamin Doron
2022-09-07 23:50 ` Isaac Oram
[not found] ` <1712B905B760092F.20378@groups.io>
2022-09-09 21:16 ` Isaac Oram
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 4/6] S3FeaturePkg: Implement working S3 resume Benjamin Doron
2022-09-08 0:38 ` Isaac Oram
2022-09-11 15:46 ` Benjamin Doron
2022-09-06 17:02 ` Benjamin Doron [this message]
2022-09-08 2:46 ` [edk2-devel][edk2-platforms][PATCH v2 5/6] MinPlatformPkg: " Isaac Oram
2022-09-06 17:02 ` [edk2-devel][edk2-platforms][PATCH v2 6/6] KabylakeOpenBoardPkg: Example of board S3 Benjamin Doron
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