From: Laszlo Ersek <lersek@redhat.com>
To: Leo Duran <leo.duran@amd.com>, edk2-devel@ml01.01.org
Cc: michael.d.kinney@intel.com, jeff.fan@intel.com, liming.gao@intel.com
Subject: Re: [v3] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
Date: Fri, 28 Oct 2016 20:42:19 +0200 [thread overview]
Message-ID: <0f424f87-02ed-18ee-3bca-395734400d37@redhat.com> (raw)
In-Reply-To: <1477676325-18717-1-git-send-email-leo.duran@amd.com>
On 10/28/16 19:38, Leo Duran wrote:
> 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
> 2) Remove ExtractProcessorLocation() from MpInitLib library.
> 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Leo Duran <leo.duran@amd.com>
> ---
> UefiCpuPkg/Include/Library/LocalApicLib.h | 18 +++
> UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++++++++++++++++++++
> .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++++++++
> UefiCpuPkg/Library/MpInitLib/MpLib.c | 128 +-------------------
> UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 121 +------------------
> 5 files changed, 280 insertions(+), 247 deletions(-)
>
> diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
> index cd4e613..4abf64c 100644
> --- a/UefiCpuPkg/Include/Library/LocalApicLib.h
> +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
> @@ -21,6 +21,9 @@
> #define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode.
> #define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode.
>
> +#include <PiPei.h>
> +#include <Protocol/MpService.h>
> +
> /**
> Retrieve the base address of local APIC.
>
> @@ -410,6 +413,21 @@ GetApicMsiValue (
> IN BOOLEAN LevelTriggered,
> IN BOOLEAN AssertionLevel
> );
> +
> +/**
> +Get Package ID/Core ID/Thread ID of a processor.
> +
> +The algorithm assumes the target system has symmetry across physical package boundaries
> +with respect to the number of logical processors per package, number of cores per package.
> +
> +@param InitialApicId Must be the initial APIC ID of the target logical processor.
> +@param Location Returns the processor location information.
> +**/
> +VOID
> +GetProcessorLocation(
> + IN UINT32 InitialApicId,
> + OUT EFI_CPU_PHYSICAL_LOCATION *Location
> +);
>
> #endif
>
> diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> index 8d0fb02..219f99f 100644
> --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> @@ -941,3 +941,133 @@ GetApicMsiValue (
> }
> return MsiData.Uint64;
> }
> +
> +/**
> +Get Package ID/Core ID/Thread ID of a processor.
> +
> +The algorithm assumes the target system has symmetry across physical package boundaries
> +with respect to the number of logical processors per package, number of cores per package.
> +
> +@param InitialApicId Must be the initial APIC ID of the target logical processor.
> +@param Location Returns the processor location information.
> +**/
> +VOID
> +GetProcessorLocation(
> +IN UINT32 InitialApicId,
> +OUT EFI_CPU_PHYSICAL_LOCATION *Location
> +)
> +{
> + BOOLEAN TopologyLeafSupported;
> + UINTN ThreadBits;
> + UINTN CoreBits;
> + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> + UINT32 MaxCpuIdIndex;
> + UINT32 SubIndex;
> + UINTN LevelType;
> + UINT32 MaxLogicProcessorsPerPackage;
> + UINT32 MaxCoresPerPackage;
> +
> + //
> + // Check if the processor is capable of supporting more than one logical processor.
> + //
> + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
> + if (VersionInfoEdx.Bits.HTT == 0) {
> + Location->Thread = 0;
> + Location->Core = 0;
> + Location->Package = 0;
> + return;
> + }
> +
> + ThreadBits = 0;
> + CoreBits = 0;
> +
> + //
> + // Assume three-level mapping of APIC ID: Package:Core:SMT.
> + //
> +
> + TopologyLeafSupported = FALSE;
> + //
> + // Get the max index of basic CPUID
> + //
> + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> +
> + //
> + // If the extended topology enumeration leaf is available, it
> + // is the preferred mechanism for enumerating topology.
> + //
> + if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> + AsmCpuidEx(
> + CPUID_EXTENDED_TOPOLOGY,
> + 0,
> + &ExtendedTopologyEax.Uint32,
> + &ExtendedTopologyEbx.Uint32,
> + &ExtendedTopologyEcx.Uint32,
> + NULL
> + );
> + //
> + // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> + // supported on that processor.
> + //
> + if (ExtendedTopologyEbx.Uint32 != 0) {
> + TopologyLeafSupported = TRUE;
> +
> + //
> + // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
> + // the SMT sub-field of x2APIC ID.
> + //
> + LevelType = ExtendedTopologyEcx.Bits.LevelType;
> + ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> + ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> +
> + //
> + // Software must not assume any "level type" encoding
> + // value to be related to any sub-leaf index, except sub-leaf 0.
> + //
> + SubIndex = 1;
> + do {
> + AsmCpuidEx(
> + CPUID_EXTENDED_TOPOLOGY,
> + SubIndex,
> + &ExtendedTopologyEax.Uint32,
> + NULL,
> + &ExtendedTopologyEcx.Uint32,
> + NULL
> + );
> + LevelType = ExtendedTopologyEcx.Bits.LevelType;
> + if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> + CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> + break;
> + }
> + SubIndex++;
> + } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> + }
> + }
> +
> + if (!TopologyLeafSupported) {
> + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> + MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> + if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> + MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> + }
> + else {
> + //
> + // Must be a single-core processor.
> + //
> + MaxCoresPerPackage = 1;
> + }
> +
> + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
> + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
> + }
> +
> + Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
> + Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> + Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
> +}
> diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> index 4c42696..16395a3 100644
> --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> @@ -1036,3 +1036,133 @@ GetApicMsiValue (
> }
> return MsiData.Uint64;
> }
> +
> +/**
> +Get Package ID/Core ID/Thread ID of a processor.
> +
> +The algorithm assumes the target system has symmetry across physical package boundaries
> +with respect to the number of logical processors per package, number of cores per package.
> +
> +@param InitialApicId Must be the initial APIC ID of the target logical processor.
> +@param Location Returns the processor location information.
> +**/
> +VOID
> +GetProcessorLocation(
> +IN UINT32 InitialApicId,
> +OUT EFI_CPU_PHYSICAL_LOCATION *Location
> +)
> +{
> + BOOLEAN TopologyLeafSupported;
> + UINTN ThreadBits;
> + UINTN CoreBits;
> + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> + UINT32 MaxCpuIdIndex;
> + UINT32 SubIndex;
> + UINTN LevelType;
> + UINT32 MaxLogicProcessorsPerPackage;
> + UINT32 MaxCoresPerPackage;
> +
> + //
> + // Check if the processor is capable of supporting more than one logical processor.
> + //
> + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
> + if (VersionInfoEdx.Bits.HTT == 0) {
> + Location->Thread = 0;
> + Location->Core = 0;
> + Location->Package = 0;
> + return;
> + }
> +
> + ThreadBits = 0;
> + CoreBits = 0;
> +
> + //
> + // Assume three-level mapping of APIC ID: Package:Core:SMT.
> + //
> +
> + TopologyLeafSupported = FALSE;
> + //
> + // Get the max index of basic CPUID
> + //
> + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> +
> + //
> + // If the extended topology enumeration leaf is available, it
> + // is the preferred mechanism for enumerating topology.
> + //
> + if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> + AsmCpuidEx(
> + CPUID_EXTENDED_TOPOLOGY,
> + 0,
> + &ExtendedTopologyEax.Uint32,
> + &ExtendedTopologyEbx.Uint32,
> + &ExtendedTopologyEcx.Uint32,
> + NULL
> + );
> + //
> + // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> + // supported on that processor.
> + //
> + if (ExtendedTopologyEbx.Uint32 != 0) {
> + TopologyLeafSupported = TRUE;
> +
> + //
> + // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
> + // the SMT sub-field of x2APIC ID.
> + //
> + LevelType = ExtendedTopologyEcx.Bits.LevelType;
> + ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> + ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> +
> + //
> + // Software must not assume any "level type" encoding
> + // value to be related to any sub-leaf index, except sub-leaf 0.
> + //
> + SubIndex = 1;
> + do {
> + AsmCpuidEx(
> + CPUID_EXTENDED_TOPOLOGY,
> + SubIndex,
> + &ExtendedTopologyEax.Uint32,
> + NULL,
> + &ExtendedTopologyEcx.Uint32,
> + NULL
> + );
> + LevelType = ExtendedTopologyEcx.Bits.LevelType;
> + if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> + CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> + break;
> + }
> + SubIndex++;
> + } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> + }
> + }
> +
> + if (!TopologyLeafSupported) {
> + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> + MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> + if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> + MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> + }
> + else {
> + //
> + // Must be a single-core processor.
> + //
> + MaxCoresPerPackage = 1;
> + }
> +
> + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
> + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
> + }
> +
> + Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
> + Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> + Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
> +}
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> index c3fe721..f3380bb 100644
> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled (
> }
>
> /**
> - Get CPU Package/Core/Thread location information.
> -
> - @param[in] InitialApicId CPU APIC ID
> - @param[out] Location Pointer to CPU location information
> -**/
> -VOID
> -ExtractProcessorLocation (
> - IN UINT32 InitialApicId,
> - OUT EFI_CPU_PHYSICAL_LOCATION *Location
> - )
> -{
> - BOOLEAN TopologyLeafSupported;
> - UINTN ThreadBits;
> - UINTN CoreBits;
> - CPUID_VERSION_INFO_EBX VersionInfoEbx;
> - CPUID_VERSION_INFO_EDX VersionInfoEdx;
> - CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> - UINT32 MaxCpuIdIndex;
> - UINT32 SubIndex;
> - UINTN LevelType;
> - UINT32 MaxLogicProcessorsPerPackage;
> - UINT32 MaxCoresPerPackage;
> -
> - //
> - // Check if the processor is capable of supporting more than one logical processor.
> - //
> - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
> - if (VersionInfoEdx.Bits.HTT == 0) {
> - Location->Thread = 0;
> - Location->Core = 0;
> - Location->Package = 0;
> - return;
> - }
> -
> - ThreadBits = 0;
> - CoreBits = 0;
> -
> - //
> - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> - //
> -
> - TopologyLeafSupported = FALSE;
> - //
> - // Get the max index of basic CPUID
> - //
> - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> -
> - //
> - // If the extended topology enumeration leaf is available, it
> - // is the preferred mechanism for enumerating topology.
> - //
> - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> - AsmCpuidEx (
> - CPUID_EXTENDED_TOPOLOGY,
> - 0,
> - &ExtendedTopologyEax.Uint32,
> - &ExtendedTopologyEbx.Uint32,
> - &ExtendedTopologyEcx.Uint32,
> - NULL
> - );
> - //
> - // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> - // supported on that processor.
> - //
> - if (ExtendedTopologyEbx.Uint32 != 0) {
> - TopologyLeafSupported = TRUE;
> -
> - //
> - // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
> - // the SMT sub-field of x2APIC ID.
> - //
> - LevelType = ExtendedTopologyEcx.Bits.LevelType;
> - ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> - ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> -
> - //
> - // Software must not assume any "level type" encoding
> - // value to be related to any sub-leaf index, except sub-leaf 0.
> - //
> - SubIndex = 1;
> - do {
> - AsmCpuidEx (
> - CPUID_EXTENDED_TOPOLOGY,
> - SubIndex,
> - &ExtendedTopologyEax.Uint32,
> - NULL,
> - &ExtendedTopologyEcx.Uint32,
> - NULL
> - );
> - LevelType = ExtendedTopologyEcx.Bits.LevelType;
> - if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> - CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> - break;
> - }
> - SubIndex++;
> - } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> - }
> - }
> -
> - if (!TopologyLeafSupported) {
> - AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> - MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> - MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> - } else {
> - //
> - // Must be a single-core processor.
> - //
> - MaxCoresPerPackage = 1;
> - }
> -
> - ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
> - CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> - }
> -
> - Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
> - Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> - Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
> -}
> -
> -/**
> Worker function for SwitchBSP().
>
> Worker function for SwitchBSP(), assigned to the AP which is intended
> @@ -1451,7 +1325,7 @@ MpInitLibGetProcessorInfo (
> //
> // Get processor location information
> //
> - ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);
> + GetProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);
>
> if (HealthData != NULL) {
> HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> index 40f2a17..67cd0a0 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService = {
> };
>
> /**
> - Get Package ID/Core ID/Thread ID of a processor.
> -
> - APIC ID must be an initial APIC ID.
> -
> - The algorithm below assumes the target system has symmetry across physical package boundaries
> - with respect to the number of logical processors per package, number of cores per package.
> -
> - @param ApicId APIC ID of the target logical processor.
> - @param Location Returns the processor location information.
> -**/
> -VOID
> -SmmGetProcessorLocation (
> - IN UINT32 ApicId,
> - OUT EFI_CPU_PHYSICAL_LOCATION *Location
> - )
> -{
> - UINTN ThreadBits;
> - UINTN CoreBits;
> - UINT32 RegEax;
> - UINT32 RegEbx;
> - UINT32 RegEcx;
> - UINT32 RegEdx;
> - UINT32 MaxCpuIdIndex;
> - UINT32 SubIndex;
> - UINTN LevelType;
> - UINT32 MaxLogicProcessorsPerPackage;
> - UINT32 MaxCoresPerPackage;
> - BOOLEAN TopologyLeafSupported;
> -
> - ASSERT (Location != NULL);
> -
> - ThreadBits = 0;
> - CoreBits = 0;
> - TopologyLeafSupported = FALSE;
> -
> - //
> - // Check if the processor is capable of supporting more than one logical processor.
> - //
> - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
> - ASSERT ((RegEdx & BIT28) != 0);
> -
> - //
> - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> - //
> -
> - //
> - // Get the max index of basic CPUID
> - //
> - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> -
> - //
> - // If the extended topology enumeration leaf is available, it
> - // is the preferred mechanism for enumerating topology.
> - //
> - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);
> - //
> - // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> - // supported on that processor.
> - //
> - if ((RegEbx & 0xffff) != 0) {
> - TopologyLeafSupported = TRUE;
> -
> - //
> - // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
> - // the SMT sub-field of x2APIC ID.
> - //
> - LevelType = (RegEcx >> 8) & 0xff;
> - ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> - if ((RegEbx & 0xffff) > 1 ) {
> - ThreadBits = RegEax & 0x1f;
> - } else {
> - //
> - // HT is not supported
> - //
> - ThreadBits = 0;
> - }
> -
> - //
> - // Software must not assume any "level type" encoding
> - // value to be related to any sub-leaf index, except sub-leaf 0.
> - //
> - SubIndex = 1;
> - do {
> - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL);
> - LevelType = (RegEcx >> 8) & 0xff;
> - if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> - CoreBits = (RegEax & 0x1f) - ThreadBits;
> - break;
> - }
> - SubIndex++;
> - } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> - }
> - }
> -
> - if (!TopologyLeafSupported) {
> - AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
> - MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
> - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
> - MaxCoresPerPackage = (RegEax >> 26) + 1;
> - } else {
> - //
> - // Must be a single-core processor.
> - //
> - MaxCoresPerPackage = 1;
> - }
> -
> - ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
> - CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> - }
> -
> - Location->Thread = ApicId & ~((-1) << ThreadBits);
> - Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
> - Location->Package = (ApicId >> (ThreadBits+ CoreBits));
> -}
> -
> -/**
> Gets processor information on the requested processor at the instant this call is made.
>
> @param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
> @@ -280,7 +161,7 @@ SmmAddProcessor (
> gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
> gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
> gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
> - SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);
> + GetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);
>
> *ProcessorNumber = Index;
> gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
>
I tested this as follows:
* X64 OVMF, build without -D SMM_REQUIRE. I retested the MSR_IA32_FEATURE_CONTROL setting feature at <https://bugzilla.tianocore.org/show_bug.cgi?id=86> (commit range 51773d4..dbab994), with S3 suspend/resume, using QEMU's i440fx machine type.
This test is relevant because it exercises EFI_PEI_MPSERVICES_PPI, provided by CpuMpPei, both at cold boot and at S3 resume. CpuMpPei in turn depends on MpInitLib. Here's the log snippet:
> Loading PEIM at 0x000BFD29000 EntryPoint=0x000BFD29240 CpuMpPei.efi
> AP Loop Mode is 1
> WakeupBufferStart = 9F000, WakeupBufferSize = 1000
> APIC MODE is 1
> MpInitLib: Find 8 processors in system.
> Register PPI Notify: [EfiEndOfPeiSignalPpi]
> Does not find any stored CPU BIST information from PPI!
> APICID - 0x00000000, BIST - 0x00000000
> APICID - 0x00000001, BIST - 0x00000000
> APICID - 0x00000002, BIST - 0x00000000
> APICID - 0x00000003, BIST - 0x00000000
> APICID - 0x00000004, BIST - 0x00000000
> APICID - 0x00000005, BIST - 0x00000000
> APICID - 0x00000006, BIST - 0x00000000
> APICID - 0x00000007, BIST - 0x00000000
> Install PPI: [EfiSecPlatformInformation2Ppi]
> Install PPI: [EfiPeiMpServicesPpi]
> Notify: PPI Guid: [EfiPeiMpServicesPpi], Peim notify entry point: 83BAC5
> PlatformPei: OnMpServicesAvailable
* Ia32X64 OVMF, built with -D SMM_REQUIRE, using the Q35 machine type. S3 suspend/resume works. SMM variable access works after resumption too, when bound to CPU#0 (BSP) or to CPU#1 (AP) alike (with "taskset -c 0/1" in the Fedora guest).
> Loading SMM driver at 0x0007FFCE000 EntryPoint=0x0007FFCE271 PiSmmCpuDxeSmm.efi
> SMRR Base: 0x7F800000, SMRR Size: 0x800000
> PcdCpuSmmCodeAccessCheckEnable = 1
> SMRAM TileSize = 0x00002000 (0x00001000, 0x00001000)
> SMRAM SaveState Buffer (0x7FFC0000, 0x0000E000)
> CPU[000] APIC ID=0000 SMBASE=7FFB8000 SaveState=7FFC7C00 Size=00000400
> CPU[001] APIC ID=0001 SMBASE=7FFBA000 SaveState=7FFC9C00 Size=00000400
> CPU[002] APIC ID=0002 SMBASE=7FFBC000 SaveState=7FFCBC00 Size=00000400
> CPU[003] APIC ID=0003 SMBASE=7FFBE000 SaveState=7FFCDC00 Size=00000400
> One Semaphore Size = 0x40
> Total Semaphores Size = 0x840
> InstallProtocolInterface: [gEfiSmmConfigurationProtocolGuid] 7FFDEFD0
> SMM IPL registered SMM Entry Point address 7FFF0A27
> SmmInstallProtocolInterface: [EfiSmmCpuProtocol] 7FFDEF10
> SmmInstallProtocolInterface: [EfiSmmCpuServiceProtocol] 7FFDEFF0
> SMM S3 SMRAM Structure = 7F0AF9C0
> SMM S3 Structure = 7F800000
> SMM CPU Module exit from SMRAM with EFI_SUCCESS
* Same as the previous point, just with the Ia32 build.
Tested-by: Laszlo Ersek <lersek@redhat.com>
Thanks
Laszlo
next prev parent reply other threads:[~2016-10-28 18:42 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-28 17:38 [v3] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library Leo Duran
2016-10-28 18:42 ` Laszlo Ersek [this message]
2016-10-28 21:12 ` Kinney, Michael D
2016-10-28 21:17 ` Duran, Leo
2016-10-28 21:48 ` Laszlo Ersek
2016-10-31 6:40 ` Fan, Jeff
2016-10-31 16:45 ` Duran, Leo
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