From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) by mx.groups.io with SMTP id smtpd.web10.6913.1623846930522371588 for ; Wed, 16 Jun 2021 05:35:31 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@akeo-ie.20150623.gappssmtp.com header.s=20150623 header.b=TYexlh5A; spf=pass (domain: akeo.ie, ip: 209.85.128.46, mailfrom: pete@akeo.ie) Received: by mail-wm1-f46.google.com with SMTP id y13-20020a1c4b0d0000b02901c20173e165so1649950wma.0 for ; Wed, 16 Jun 2021 05:35:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=akeo-ie.20150623.gappssmtp.com; s=20150623; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=z0Wz7crGlLjDK8LJIimU8+urLBvZHypA4nn6PmzH4yQ=; b=TYexlh5A84OADnSAy3r9E431Fz2SB5eDcJqYux8+KdBfMwf6pvudQkdFbz+KdMWaQS BR2sFxxLxurn2cn26lkChHN3Vd9Esfo3GvwW6Xa6V+3TB36woLVFBIWG+wcyukF1lJc3 4Pdl2SvA/PiCyMY8A2Y9pPPrDj9Q5pKENO1xMYG1oJ6U3/rWLDn4x+x/cQMZ+Rr/BqFo Muh4qLtpksruQ5iKqA8crEM0xMuZIuSjVYS3SinfxGVfKmR25aqHdIkPhXlNlf+bLgeU syI2QAafydQFrIRkaQoiRH4cTJ0mQtPZkpuSzQCT5dXIY0R0vaip8x+PXwiz9lHSxh63 yTVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=z0Wz7crGlLjDK8LJIimU8+urLBvZHypA4nn6PmzH4yQ=; b=cYTw9Jm9pPAXEQdoNueDKw8TPdZT2DyI65EJpNVNVRhEbO/QYLwIsgnPbKB5hwPJZc ZsjTI1xgkdajV4QBIVbDkluPKGmwEdpYwah2Vip2LbUKDJiPWVRcaZ/cDDJGX33PWdsE wdRRBvHBVyoP5Xf/0HnlkifBe+inGHUcJsquyi3X3BKYUZSRUNxlOtGduypRj2a6ZIBA H0fKJLw/VLrEtXVwP8NLCW6uZxNjnCeO7AFgX0f9x+oOsRxsX1guvuBZK4hOMpGGrR/c MrNWo6FYoD5fh6kfkBikXxyuoMV/1Ehoc0EzK/h67qCd7K3YAaii+iuDWf7HBAZGqOjX 8okw== X-Gm-Message-State: AOAM531aTcAiPR57KPgPXXQMMAwXys701vYDNFb9skijhW37JYCwpuM7 fP/dO4uClw1pGU+i7DmgTqGlsA== X-Google-Smtp-Source: ABdhPJx01Vx2FTUm2vctzFwfsSCeIWAKxBBIDH3jFTBYpACz38bEoFHWysHLBlxvXrIk4ssXFgLUJw== X-Received: by 2002:a05:600c:35c3:: with SMTP id r3mr11053920wmq.169.1623846929000; Wed, 16 Jun 2021 05:35:29 -0700 (PDT) Return-Path: Received: from [10.0.0.122] ([84.203.66.113]) by smtp.googlemail.com with ESMTPSA id o7sm2071690wro.76.2021.06.16.05.35.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Jun 2021 05:35:28 -0700 (PDT) Subject: Re: [edk2-devel] [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations To: devel@edk2.groups.io, daniel.schaefer@hpe.com, Sunil V L Cc: "Chang, Abner (HPS SW/FW Technologist)" , Bob Feng , Liming Gao , Yuwei Chen , Heinrich Schuchardt References: <20210611140503.28409-1-sunilvl@ventanamicro.com> <20210611140807.GA28471@sunil-ThinkPad-T490> From: "Pete Batard" Message-ID: <0fb7313d-9050-cb00-c378-a983a7c80855@akeo.ie> Date: Wed, 16 Jun 2021 13:35:27 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 8bit Sunil, Daniel, thanks for the patch. I confirm that this addresses the 0x13 and 0x14 relocation issues that I was seeing. However, this patch appears to introduces new R_RISCV_PCREL_LO12_S relocation errors that I was not seeing previously, so I still can't manage to get a successful compilation. Especially the stream of 0x13 and 0x14 relocation errors I was getting at https://github.com/pbatard/ntfs-3g/runs/2278190652?check_suite_focus=true has now switched to (tested on up to date Ubuntu with latest EDK2): ------------------------------------------------------------------------- "GenFw" -e UEFI_DRIVER -o /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/OUTPUT/ntfs.efi /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll GenFw: ERROR 3000: Invalid WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll unsupported ELF EM_RISCV64 relocation 0x19. GenFw: ERROR 3000: Invalid WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll unsupported ELF EM_RISCV64 relocation 0x19. GenFw: ERROR 3000: Invalid WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll unsupported ELF EM_RISCV64 relocation 0x19. GenFw: ERROR 3000: Invalid WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll unsupported ELF EM_RISCV64 relocation 0x19. GenFw: ERROR 3000: Invalid WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll unsupported ELF EM_RISCV64 relocation 0x19. GenFw: ERROR 3000: Invalid WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll unsupported ELF EM_RISCV64 relocation 0x19. make: *** [GNUmakefile:553: /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/OUTPUT/ntfs.efi] Error 2 ------------------------------------------------------------------------- So, in effect, some of the earlier relocation errors appear to have morphed into 0x19/R_RISCV_PCREL_LO12_S ones... I can open a new bug for this issue if you prefer. Regards, /Pete On 2021.06.15 03:26, Daniel Schaefer wrote: > Great commit message, thanks Sunil! > Maintainers, please take a look and let us know if there's any other > concern. > This patch lets us build the RISC-V platforms using modern toolchains > that are provided directly by the distributions, rather than building > your own from source. > > Thanks, > Daniel > ------------------------------------------------------------------------ > *From:* Sunil V L > *Sent:* Friday, June 11, 2021 22:08 > *To:* devel@edk2.groups.io > *Cc:* Chang, Abner (HPS SW/FW Technologist) ; > Schaefer, Daniel ; Bob Feng > ; Liming Gao ; Yuwei > Chen ; Heinrich Schuchardt > *Subject:* Re: [RESEND PATCH v2] BaseTools: Add support for RISCV > GOT/PLT relocations > Hi, >     I just edited the commit message to indicate the module and CC the >     maintainers. Could I get the feedback please? > Thanks > Sunil > > On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote: >> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096 > >> >> This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20 >> relocations generated by PIE enabled compiler. This also needed >> changes to R_RISCV_32 and R_RISCV_64 relocations as explained in >> https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710 > >> >> Changes in v2: >>   - Addressed Daniel's comment on formatting >> >> Testing: >> 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models. >> 2) Debian 10.2.0 and booted QEMU virt model. >> 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model. >> >> Signed-off-by: Sunil V L >> >> Acked-by: Abner Chang >> Reviewed-by: Daniel Schaefer >> Tested-by: >> >> Cc: Bob Feng >> Cc: Liming Gao >> Cc: Yuwei Chen >> Cc: Heinrich Schuchardt >> --- >>  BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++---- >>  1 file changed, 38 insertions(+), 6 deletions(-) >> >> diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c >> index d097db8632..d684318269 100644 >> --- a/BaseTools/Source/C/GenFw/Elf64Convert.c >> +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c >> @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset; >>  STATIC UINT8       *mRiscVPass1Targ = NULL; >>  STATIC Elf_Shdr    *mRiscVPass1Sym = NULL; >>  STATIC Elf64_Half  mRiscVPass1SymSecIndex = 0; >> +STATIC INT32       mRiscVPass1Offset; >> +STATIC INT32       mRiscVPass1GotFixup; >> >>  // >>  // Initialization Function >> @@ -479,11 +481,11 @@ WriteSectionRiscV64 ( >>      break; >> >>    case R_RISCV_32: >> -    *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]); >> +    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend; >>      break; >> >>    case R_RISCV_64: >> -    *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]; >> +    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend; >>      break; >> >>    case R_RISCV_HI20: >> @@ -533,6 +535,18 @@ WriteSectionRiscV64 ( >>      mRiscVPass1SymSecIndex = 0; >>      break; >> >> +  case R_RISCV_GOT_HI20: >> +    Value = (Sym->st_value - Rel->r_offset); >> +    mRiscVPass1Offset = RV_X(Value, 0, 12); >> +    Value = RV_X(Value, 12, 20); >> +    *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12)); >> + >> +    mRiscVPass1Targ = Targ; >> +    mRiscVPass1Sym = SymShdr; >> +    mRiscVPass1SymSecIndex = Sym->st_shndx; >> +    mRiscVPass1GotFixup = 1; >> +    break; >> + >>    case R_RISCV_PCREL_HI20: >>      mRiscVPass1Targ = Targ; >>      mRiscVPass1Sym = SymShdr; >> @@ -545,11 +559,17 @@ WriteSectionRiscV64 ( >>      if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) { >>        int i; >>        Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20)); >> -      Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); >> -      if(Value & (RISCV_IMM_REACH/2)) { >> -        Value |= ~(RISCV_IMM_REACH-1); >> + >> +      if(mRiscVPass1GotFixup) { >> +        Value = (UINT32)(mRiscVPass1Offset); >> +      } else { >> +        Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12)); >> +        if(Value & (RISCV_IMM_REACH/2)) { >> +          Value |= ~(RISCV_IMM_REACH-1); >> +        } >>        } >>        Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex]; >> + >>        if(-2048 > (INT32)Value) { >>          i = (((INT32)Value * -1) / 4096); >>          Value2 -= i; >> @@ -569,12 +589,21 @@ WriteSectionRiscV64 ( >>          } >>        } >> >> -      *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20)); >> +      if(mRiscVPass1GotFixup) { >> +        *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20) >> +                            | (RV_X(*(UINT32*)Targ, 0, 20)); >> +        /* Convert LD instruction to ADDI */ >> +        *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13); >> +      } else { >> +        *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20)); >> +      } >>        *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12)); >>      } >>      mRiscVPass1Sym = NULL; >>      mRiscVPass1Targ = NULL; >>      mRiscVPass1SymSecIndex = 0; >> +    mRiscVPass1Offset = 0; >> +    mRiscVPass1GotFixup = 0; >>      break; >> >>    case R_RISCV_ADD64: >> @@ -586,6 +615,7 @@ WriteSectionRiscV64 ( >>    case R_RISCV_GPREL_I: >>    case R_RISCV_GPREL_S: >>    case R_RISCV_CALL: >> +  case R_RISCV_CALL_PLT: >>    case R_RISCV_RVC_BRANCH: >>    case R_RISCV_RVC_JUMP: >>    case R_RISCV_RELAX: >> @@ -1528,6 +1558,7 @@ WriteRelocations64 ( >>              case R_RISCV_GPREL_I: >>              case R_RISCV_GPREL_S: >>              case R_RISCV_CALL: >> +            case R_RISCV_CALL_PLT: >>              case R_RISCV_RVC_BRANCH: >>              case R_RISCV_RVC_JUMP: >>              case R_RISCV_RELAX: >> @@ -1537,6 +1568,7 @@ WriteRelocations64 ( >>              case R_RISCV_SET16: >>              case R_RISCV_SET32: >>              case R_RISCV_PCREL_HI20: >> +            case R_RISCV_GOT_HI20: >>              case R_RISCV_PCREL_LO12_I: >>                break; >> >> -- >> 2.25.1 >> >