Re: [edk2-devel] [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock

["Laszlo Ersek" <lersek@redhat.com>]

On 09/18/19 17:43, John E Lofgren wrote:
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150
> V3 changes:
> change to mov instruction (non locking instuction) instead
> of xchg to simplify design.

This patch should have been posted as "v4" actually -- it differs from
what you originally posted as v3. Therefore it cannot be considered v3.

The changelog in the patch would say,

v4:
The v3 posting didn't do what it promised to do, so do it now for real.

v3:
<whatever it originally said>

Anyway, not a deal breaker. More comments below.

> V2 changes:
> Add xchg 16 bit instructions to handle sgdt and sidt base
> 63:48 bits and 47:32 bits.
> Add comment to explain why xchg 64bit isnt being used
> 
> Split lock happens when a locking instruction is used on mis-aligned data
> that crosses two cachelines. If close source platform enables Alignment Check
> Exception(#AC), They can hit a double fault due to split lock being in
> CpuExceptionHandlerLib.
> 
> sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit.
> The data is mis-aligned, can cross two cacheline, and a xchg
> instruction(locking instuction) is being utilize.
> 
> Signed-off-by: John E Lofgren <john.e.lofgren@intel.com>
> ---
>  UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
> index 4db1a09f28..19198f2731 100644
> --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
> +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
> @@ -184,17 +184,19 @@ HasErrorCode:
>      push    rax
>      push    rax
>      sidt    [rsp]
> -    xchg    rax, [rsp + 2]
> -    xchg    rax, [rsp]
> -    xchg    rax, [rsp + 8]
> +    mov     bx, word [rsp]
> +    mov     rax, qword [rsp + 2]
> +    mov     qword [rsp], rax
> +    mov     word [rsp + 8], bx
>  
>      xor     rax, rax
>      push    rax
>      push    rax
>      sgdt    [rsp]
> -    xchg    rax, [rsp + 2]
> -    xchg    rax, [rsp]
> -    xchg    rax, [rsp + 8]
> +    mov     bx, word [rsp]
> +    mov     rax, qword [rsp + 2]
> +    mov     qword [rsp], rax
> +    mov     word [rsp + 8], bx
>  
>  ;; UINT64  Ldtr, Tr;
>      xor     rax, rax
> 

I think it would be nice to learn why XCHG was used in the first place.
Then again, whatever it was preferred for, it could not have been
locking, as the three XCHG instructions are not atomic as a whole (i.e.
they are not locked all together).

Another reason for XCHG could be that they wanted to use just one
register -- but I totally don't see the point of not using BX too.

So:

Reviewed-by: Laszlo Ersek <lersek@redhat.com>

Thanks,
Laszlo