From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web09.9187.1653688037094986564 for ; Fri, 27 May 2022 14:47:18 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=km0Mal+v; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: isaac.w.oram@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653688037; x=1685224037; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s7uXfEDtenmsb40GVsvIqB9r5wu/QaWHMyxnHcKHplE=; b=km0Mal+vxMNmC/T7k5lPUrvrNj3bNcHPQ5D/NpJd18aYON71jTaVSjmX dEGE8gN5KNqiz8ROMlGA4AkDntgsKnSP2PTZac5Vres1F8BZG7MvYBbk2 l11zbMffcH38kDAicdsI+NOaUIXWto9UTw2IAAaLyvdP+qqdO9vIe1ar4 gaMdYmIeOh/c+9lCo/dUTbdrozYB/AS9UTl9S2D77n3m9XZWyVfP2omhz uwrwFxPM7kUlIaNsWc0EZyOwj8Xn8L94sCUrjTSC3UfcaPC9fLkwwo+v/ hb4BSXrGM0HN9dNykxV1WT07DlOe49NcHaKD2Vv3DbfP0PoegL1Gpw03k w==; X-IronPort-AV: E=McAfee;i="6400,9594,10360"; a="274310955" X-IronPort-AV: E=Sophos;i="5.91,256,1647327600"; d="scan'208";a="274310955" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2022 14:47:16 -0700 X-IronPort-AV: E=Sophos;i="5.91,256,1647327600"; d="scan'208";a="631785758" Received: from iworam-desk.amr.corp.intel.com ([10.24.80.243]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 May 2022 14:47:16 -0700 From: "Oram, Isaac W" To: devel@edk2.groups.io Cc: Nate DeSimone , Chasel Chiu Subject: [edk2-devel][edk2-platforms][PATCH V1 1/1] WhitleySiliconPkg/PchPolicyPpi: Fix binary structure layout Date: Fri, 27 May 2022 14:47:05 -0700 Message-Id: <0ff4a7949acbaf1fe3ef51ba358bd6b8358339f9.1653687365.git.isaac.w.oram@intel.com> X-Mailer: git-send-email 2.36.1.windows.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Disambiguate the PCH_DMI_CONFIG and PCH_TRACE_HUB_CONFIG structure definitions such that compilers generate same binary layouts. Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram --- .../Pch/SouthClusterLbg/Include/PchPolicyCommon.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h index 0e10d0b8f0..c95481bf1d 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h +++ b/Silicon/Intel/WhitleySiliconPkg/Pch/SouthClusterLbg/Include/PchPolicyCommon.h @@ -1351,7 +1351,9 @@ typedef struct { **/ UINT32 DmiAspm : 1; UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable DMI Power Optimizer on PCH side. + UINT32 Rsvdbits1 : 30; BOOLEAN DmiStopAndScreamEnable : 1; + BOOLEAN Rsvdbits2 : 7; UINT32 DmiLinkDownHangBypass : 1; UINT32 Rsvdbits : 29; UINT32 Rsvd0[6]; ///< Reserved bytes @@ -1447,6 +1449,7 @@ typedef struct { TRACE_HUB_CONFIG TraceHub; UINT32 AetEnableMode : 2; UINT32 PchTraceHubHide : 1; + UINT32 Rsvdbits : 29; } PCH_TRACE_HUB_CONFIG; -- 2.36.1.windows.1