* [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms
@ 2021-04-28 12:12 Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 1/8] Platform/Sgi: Helper macros for PPTT Table Pranav Madhu
` (9 more replies)
0 siblings, 10 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-28 12:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Pierre Gondois, Sami Mujawar
Changes since V1:
- Rebase the patches on top of latest master branch
- Addressed comments from Pierre
Processor Properties Topology Table (PPTT) describes the topological
structure of processors, and their shared resources such as caches.
This patch series adds PPTT table for Arm's Neoverse Reference Design
platforms.
The first patch in this series adds helper macros for PPTT table, and
the subsequent patches in this series adds PPTT table for Neoverse
Reference Design platforms which is mandatory as per Arm SystemReady SR
specification.
Link to github branch with the patches in this series -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_pptt
Pranav Madhu (8):
Platform/Sgi: Helper macros for PPTT Table
Platform/Sgi: ACPI PPTT table for SGI-575 platform
Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform
Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip
Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
Platform/Sgi: ACPI PPTT Table for RD-V1 platform
Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform
Platform/Sgi: ACPI PPTT table for RD-N2 platform
.../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +-
.../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +-
.../AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
.../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +-
.../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +-
.../SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 +
.../SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 160 ++++++++++++
.../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 230 ++++++++++++++++++
.../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 175 +++++++++++++
.../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 192 +++++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 163 +++++++++++++
Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 164 +++++++++++++
.../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 169 +++++++++++++
.../ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 161 ++++++++++++
15 files changed, 1426 insertions(+), 5 deletions(-)
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
--
2.17.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 1/8] Platform/Sgi: Helper macros for PPTT Table
2021-04-28 12:12 [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
@ 2021-04-28 12:12 ` Pranav Madhu
2021-05-10 8:43 ` Sami Mujawar
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform Pranav Madhu
` (8 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Pranav Madhu @ 2021-04-28 12:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Pierre Gondois, Sami Mujawar
Add helper macros for the creation for PPTT table. These macros help
with initializing processor hierarchy node structure, cache type
structure and ID structure.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
| 160 ++++++++++++++++++++
1 file changed, 160 insertions(+)
--git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
index dcb4e6c77a74..7bb8b6dec6a3 100644
--- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
+++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
@@ -20,6 +20,131 @@
#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
+#define CORE_COUNT FixedPcdGet32 (PcdCoreCount)
+#define CLUSTER_COUNT FixedPcdGet32 (PcdClusterCount)
+
+#pragma pack(1)
+// PPTT processor core structure
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 ResourceOffset[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+} RD_PPTT_CORE;
+
+// PPTT processor cluster structure
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 ResourceOffset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ RD_PPTT_CORE Core[CORE_COUNT];
+} RD_PPTT_CLUSTER;
+
+// PPTT processor cluster structure without cache
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ RD_PPTT_CORE Core[CORE_COUNT];
+} RD_PPTT_MINIMAL_CLUSTER;
+
+// PPTT processor package structure
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 ResourceOffset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT];
+} RD_PPTT_SLC_PACKAGE;
+#pragma pack ()
+
+//
+// PPTT processor structure flags for different SoC components as defined in
+// ACPI 6.3 specification
+//
+
+// Processor structure flags for SoC package
+#define PPTT_PROCESSOR_PACKAGE_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ }
+
+// Processor structure flags for cluster
+#define PPTT_PROCESSOR_CLUSTER_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ }
+
+// Processor structure flags for single-thread core
+#define PPTT_PROCESSOR_CORE_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF \
+ }
+
+// Processor structure flags for multi-thread core
+#define PPTT_PROCESSOR_CORE_THREADED_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
+ EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
+ }
+
+// Processor structure flags for CPU thread
+#define PPTT_PROCESSOR_THREAD_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, \
+ EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD, \
+ EFI_ACPI_6_3_PPTT_NODE_IS_LEAF \
+ }
+
+// PPTT cache structure flags as defined in ACPI 6.3 Specification
+#define PPTT_CACHE_STRUCTURE_FLAGS \
+ { \
+ EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID, \
+ EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID, \
+ EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID, \
+ EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID, \
+ EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID, \
+ EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID, \
+ EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID \
+ }
+
+// PPTT cache attributes for data cache
+#define PPTT_DATA_CACHE_ATTR \
+ { \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
+ }
+
+// PPTT cache attributes for instruction cache
+#define PPTT_INST_CACHE_ATTR \
+ { \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
+ }
+
+// PPTT cache attributes for unified cache
+#define PPTT_UNIFIED_CACHE_ATTR \
+ { \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
+ EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
+ }
+
// A macro to initialise the common header part of EFI ACPI tables as defined by
// EFI_ACPI_DESCRIPTION_HEADER structure.
#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
@@ -246,4 +371,39 @@
TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
}
+// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR
+#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag, Parent, \
+ ACPIProcessorID, NumberOfPrivateResource) \
+ { \
+ EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type 0 */ \
+ Length, /* Length */ \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ }, \
+ Flag, /* Processor flags */ \
+ Parent, /* Ref to parent node */ \
+ ACPIProcessorID, /* UID, as per MADT */ \
+ NumberOfPrivateResource /* Resource count */ \
+ }
+
+// EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE
+#define EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache, Size, \
+ NoOfSets, Associativity, Attributes, LineSize) \
+ { \
+ EFI_ACPI_6_3_PPTT_TYPE_CACHE, /* Type 1 */ \
+ sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), /* Length */ \
+ { \
+ EFI_ACPI_RESERVED_BYTE, \
+ EFI_ACPI_RESERVED_BYTE, \
+ }, \
+ Flag, /* Cache flags */ \
+ NextLevelCache, /* Ref to next level */ \
+ Size, /* Size in bytes */ \
+ NoOfSets, /* Num of sets */ \
+ Associativity, /* Num of ways */ \
+ Attributes, /* Cache attributes */ \
+ LineSize /* Line size in bytes */ \
+ }
+
#endif /* __SGI_ACPI_HEADER__ */
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform
2021-04-28 12:12 [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 1/8] Platform/Sgi: Helper macros for PPTT Table Pranav Madhu
@ 2021-04-28 12:12 ` Pranav Madhu
2021-05-10 8:43 ` Sami Mujawar
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 3/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform Pranav Madhu
` (7 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Pranav Madhu @ 2021-04-28 12:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Pierre Gondois, Sami Mujawar
From: Pranav Madhu <Pranav.Madhu@arm.com>
The SGI-575 platform includes two clusters with four single-thread CPUs.
Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache
and 512KB L2 cache. Each cluster includes a 2MB L3 cache. Add PPTT table
for SGI-575 platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 161 ++++++++++++++++++++
2 files changed, 163 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
index 2121fd39f2f0..b1ee16e98ea3 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018, ARM Ltd. All rights reserved.
+# Copyright (c) 2018 - 2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,6 +22,7 @@
Mcfg.aslc
Sgi575/Dsdt.asl
Sgi575/Madt.aslc
+ Sgi575/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
new file mode 100644
index 000000000000..3388a012dd55
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
@@ -0,0 +1,161 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for SGI-575 platform
+*
+* This file describes the topological structure of the processor block on the
+* SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-575
+* platform includes two clusters with four single-thread CPUS. Each of the CPUs
+* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache.
+* Each cluster includes a 2MB L3 cache.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define PPTT_CORE_INIT(pid, cid, cpuid) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid]), /* Parent */ \
+ ((pid << 3) | (cid << 2) | cpuid), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 64, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_512KB, /* Size */ \
+ 1024, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), \
+ /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].L3Cache), \
+ \
+ /* L3 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Initialize child cores */ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0), \
+ PPTT_CORE_INIT (pid, cid, 1), \
+ PPTT_CORE_INIT (pid, cid, 2), \
+ PPTT_CORE_INIT (pid, cid, 3) \
+ } \
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} SGI575_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ SGI575_PPTT_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (SGI575_PPTT_PACKAGE, Cluster[0]),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0
+ ),
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1)
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 3/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform
2021-04-28 12:12 [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 1/8] Platform/Sgi: Helper macros for PPTT Table Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform Pranav Madhu
@ 2021-04-28 12:12 ` Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 4/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip Pranav Madhu
` (6 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-28 12:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Pierre Gondois, Sami Mujawar
The RD-N1-Edge platform includes two clusters with four single-thread
CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
cache and 512KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-N1-Edge platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 175 ++++++++++++++++++++
2 files changed, 177 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
index 22e33239070b..eecb64186473 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdN1Edge/Dsdt.asl
RdN1Edge/Madt.aslc
+ RdN1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
new file mode 100644
index 000000000000..1a9dc1762767
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
@@ -0,0 +1,175 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N1-Edge single-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N1-Edge single-chip platform in the form as defined by ACPI PPTT table. The
+* RD-N1-Edge platform includes two clusters with four single-thread CPUS. Each
+* of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2
+* cache. Each cluster includes a 2MB L3 cache. The platform also includes a
+* system level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define PPTT_CORE_INIT(pid, cid, cpuid) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid]), /* Parent */ \
+ ((pid << 3) | (cid << 2) | cpuid), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_512KB, /* Size */ \
+ 1024, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].L3Cache), \
+ \
+ /* L3 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Initialize child cores */ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0), \
+ PPTT_CORE_INIT (pid, cid, 1), \
+ PPTT_CORE_INIT (pid, cid, 2), \
+ PPTT_CORE_INIT (pid, cid, 3) \
+ } \
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDN1EDGE_PPTT_PACKAGE ;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDN1EDGE_PPTT_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (RDN1EDGE_PPTT_PACKAGE , Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_8MB, /* Size */
+ 8192, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64 /* Line size */
+ ),
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 4/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip
2021-04-28 12:12 [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (2 preceding siblings ...)
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 3/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform Pranav Madhu
@ 2021-04-28 12:12 ` Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Pranav Madhu
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-28 12:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Pierre Gondois, Sami Mujawar
The RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip
platforms connected over cache coherent interconnect. Each of the
RD-N1-Edge single-chip platform includes two clusters with four
single-thread CPUs. Each of the CPUs include 64KB L1 Data cache, 64KB
L1 Instruction cache and 512KB L2 cache. Each cluster includes a 2MB
L3 cache. The platform also includes a system level cache of 8MB per
chip. Add PPTT table for RD-N1-Edge dual-chip platform with this
information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 192 ++++++++++++++++++++
2 files changed, 193 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
index 76886d1c6a17..91d219d14506 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2AcpiTables.inf
@@ -24,6 +24,7 @@
RdN1Edge/Dsdt.asl
RdN1EdgeX2/Hmat.aslc
RdN1EdgeX2/Madt.aslc
+ RdN1EdgeX2/Pptt.aslc
RdN1EdgeX2/Srat.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
new file mode 100644
index 000000000000..d1bf30dc21c7
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
@@ -0,0 +1,192 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N1-Edge dual-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N1-Edge dual-chip platform in the form as defined by ACPI PPTT table. The
+* RD-N1-Edge dual-chip platform includes two RD-N1-Edge single-chip platforms
+* connected over cache coherent interconnect. Each of the RD-N1-Edge single-chip
+* platform includes two clusters with four single-thread CPUS. Each of the CPUs
+* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache. Each
+* cluster includes a 2MB L3 cache. Each instance of the chip includes a system
+* level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
+
+#define PPTT_CORE_INIT(pid, cid, cpuid) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid]), /* Parent */ \
+ ((pid << 3) | (cid << 2) | cpuid), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[cpuid].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[cpuid].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_512KB, /* Size */ \
+ 1024, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid]), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].L3Cache), \
+ \
+ /* L3 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Initialize child cores */ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0), \
+ PPTT_CORE_INIT (pid, cid, 1), \
+ PPTT_CORE_INIT (pid, cid, 2), \
+ PPTT_CORE_INIT (pid, cid, 3) \
+ } \
+ }
+
+#define PPTT_PACKAGE_INIT(pid) \
+ { \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RDN1EDGEX2_PPTT_PACKAGE , Slc), /* Length */ \
+ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \
+ 0, /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Slc), \
+ \
+ /* SLC parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_8MB, /* Size */ \
+ 8192, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ { \
+ PPTT_CLUSTER_INIT (pid, 0), \
+ PPTT_CLUSTER_INIT (pid, 1), \
+ } \
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDN1EDGEX2_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDN1EDGEX2_PPTT_PACKAGE Package[CHIP_COUNT];
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ PPTT_PACKAGE_INIT (0),
+ PPTT_PACKAGE_INIT (1)
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
2021-04-28 12:12 [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (3 preceding siblings ...)
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 4/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip Pranav Madhu
@ 2021-04-28 12:12 ` Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 6/8] Platform/Sgi: ACPI PPTT Table for RD-V1 platform Pranav Madhu
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-28 12:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Pierre Gondois, Sami Mujawar
The RD-E1-Edge platform includes two clusters with eight multi-thread
CPUs. Each of the CPUs include 32KB L1 Data cache, 32KB L1 Instruction
cache and 256KB L2 cache. Each cluster includes a 2MB L3 cache. The
platform also includes a system level cache of 8MB. Add PPTT table for
RD-E1-Edge platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 230 ++++++++++++++++++++
2 files changed, 232 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
index 2dd2275665a2..04ef2bfcaa26 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2018-2020, ARM Ltd. All rights reserved.
+# Copyright (c) 2018-2021, ARM Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdE1Edge/Dsdt.asl
RdE1Edge/Madt.aslc
+ RdE1Edge/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
new file mode 100644
index 000000000000..d4c7b1613a28
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
@@ -0,0 +1,230 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-E1-Edge platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-E1-Edge platform in the form as defined by ACPI PPTT table. The RD-E1-Edge
+* platform includes two clusters with eight dual-thread CPUS. Each of the CPUs
+* include 32KB L1 Data cache, 32KB L1 Instruction cache and 256KB L2 cache.
+* Each cluster includes a 2MB L3 cache. The platform also includes a system
+* level cache of 8MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define THREAD_PER_CORE_E1 2
+
+#define PPTT_THREAD_INIT(pid, cid, cpuid, tid) \
+ { \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ sizeof (RDE1EDGE_PPTT_THREAD), /* Length */ \
+ PPTT_PROCESSOR_THREAD_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid]), /* Parent */ \
+ ((pid << 5) | (cid << 4) | (cpuid << 1) | tid), \
+ /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ) \
+ }
+
+#define PPTT_CORE_INIT(pid, cid, cpuid) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RDE1EDGE_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_THREADED_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid]), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_32KB, /* Size */ \
+ 128, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_32KB, /* Size */ \
+ 128, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_256KB, /* Size */ \
+ 1024, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Thread Initialization */ \
+ { \
+ PPTT_THREAD_INIT (pid, cid, cpuid, 0), \
+ PPTT_THREAD_INIT (pid, cid, cpuid, 1) \
+ } \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RDE1EDGE_PPTT_CLUSTER, L3Cache), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].L3Cache), \
+ \
+ /* L3 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_2MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* Initialize child cores */ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0), \
+ PPTT_CORE_INIT (pid, cid, 1), \
+ PPTT_CORE_INIT (pid, cid, 2), \
+ PPTT_CORE_INIT (pid, cid, 3), \
+ PPTT_CORE_INIT (pid, cid, 4), \
+ PPTT_CORE_INIT (pid, cid, 5), \
+ PPTT_CORE_INIT (pid, cid, 6), \
+ PPTT_CORE_INIT (pid, cid, 7) \
+ } \
+ }
+
+#define PPTT_PACKAGE_INIT(pid) \
+ { \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RDE1EDGE_PPTT_PACKAGE, Slc), \
+ PPTT_PROCESSOR_PACKAGE_FLAGS, \
+ 0, \
+ 0, \
+ 1 \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Slc), \
+ \
+ /* SLC parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_8MB, /* Size */ \
+ 8192, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ { \
+ PPTT_CLUSTER_INIT (pid, 0), \
+ PPTT_CLUSTER_INIT (pid, 1), \
+ } \
+ }
+
+#pragma pack(1)
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Thread;
+} RDE1EDGE_PPTT_THREAD;
+
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
+ UINT32 Offset[2];
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
+ RDE1EDGE_PPTT_THREAD Thread[THREAD_PER_CORE_E1];
+} RDE1EDGE_PPTT_CORE;
+
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
+ RDE1EDGE_PPTT_CORE Core[CORE_COUNT / THREAD_PER_CORE_E1];
+} RDE1EDGE_PPTT_CLUSTER;
+
+typedef struct {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
+ UINT32 Offset;
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
+ RDE1EDGE_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
+} RDE1EDGE_PPTT_PACKAGE;
+
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RDE1EDGE_PPTT_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ PPTT_PACKAGE_INIT (0)
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 6/8] Platform/Sgi: ACPI PPTT Table for RD-V1 platform
2021-04-28 12:12 [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (4 preceding siblings ...)
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Pranav Madhu
@ 2021-04-28 12:12 ` Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 7/8] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform Pranav Madhu
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-28 12:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Pierre Gondois, Sami Mujawar
The RD-V1 platform includes sixteen single-thread CPUs. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB
L2 cache. The platform also includes a system level cache of 16MB.
Add PPTT table for RD-V1 platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 164 ++++++++++++++++++++
2 files changed, 166 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
index a21dcfafef1a..a3e558cf1535 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,6 +23,7 @@
Mcfg.aslc
RdV1/Dsdt.asl
RdV1/Madt.aslc
+ RdV1/Pptt.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
new file mode 100644
index 000000000000..1c157e3bee2e
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
@@ -0,0 +1,164 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-V1 single-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-V1 single-chip platform in the form as defined by ACPI PPTT table. The
+* RD-V1 single-chip platform includes sixteen single-thread CPUS. Each of the
+* CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache.
+* The platform also includes a system level cache of 16MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define PPTT_CORE_INIT(pid, cid, cpuid) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid]), /* Parent */ \
+ ((pid << 4) | cid), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_1MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ), \
+ \
+ /* Initialize child core */ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0) \
+ } \
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_16MB, /* Size */
+ 16384, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64 /* Line size */
+ ),
+
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ PPTT_CLUSTER_INIT (0, 2),
+ PPTT_CLUSTER_INIT (0, 3),
+ PPTT_CLUSTER_INIT (0, 4),
+ PPTT_CLUSTER_INIT (0, 5),
+ PPTT_CLUSTER_INIT (0, 6),
+ PPTT_CLUSTER_INIT (0, 7),
+ PPTT_CLUSTER_INIT (0, 8),
+ PPTT_CLUSTER_INIT (0, 9),
+ PPTT_CLUSTER_INIT (0, 10),
+ PPTT_CLUSTER_INIT (0, 11),
+ PPTT_CLUSTER_INIT (0, 12),
+ PPTT_CLUSTER_INIT (0, 13),
+ PPTT_CLUSTER_INIT (0, 14),
+ PPTT_CLUSTER_INIT (0, 15)
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 7/8] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform
2021-04-28 12:12 [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (5 preceding siblings ...)
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 6/8] Platform/Sgi: ACPI PPTT Table for RD-V1 platform Pranav Madhu
@ 2021-04-28 12:12 ` Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 8/8] Platform/Sgi: ACPI PPTT table for RD-N2 platform Pranav Madhu
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-28 12:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Pierre Gondois, Sami Mujawar
The RD-V1 quad-chip platform consists of four chips connected over cache
coherent interconnect. Each chip on the platform includes four single-
thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1
Instruction cache and 1MB L2 cache. The platform also includes a system
level cache of 16MB per chip. Add PPTT table for RD-V1 quad-chip
platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 169 ++++++++++++++++++++
2 files changed, 170 insertions(+)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
index c49546ec0b27..ffda4f925b19 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1McAcpiTables.inf
@@ -24,6 +24,7 @@
RdV1Mc/Dsdt.asl
RdV1Mc/Hmat.aslc
RdV1Mc/Madt.aslc
+ RdV1Mc/Pptt.aslc
RdV1Mc/Srat.aslc
Spcr.aslc
Ssdt.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
new file mode 100644
index 000000000000..5e35871b068b
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
@@ -0,0 +1,169 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. The RD-V1
+* quad-chip platform is composed of four identical chips connected over cache
+* coherent interconnect. Each of the chip on the platform includes four single
+* thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction
+* cache and 1MB L2 cache. The platform also includes a system level cache of
+* 16MB per chip.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
+
+#define PPTT_CORE_INIT(pid, cid, cpuid) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid]), /* Parent */ \
+ ((pid << 2) | cid), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[cpuid].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[cpuid].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_1MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid]), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ), \
+ \
+ /* Initialize child core */ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0) \
+ } \
+ }
+
+#define PPTT_PACKAGE_INIT(pid) \
+ { \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), /* Length */ \
+ PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ \
+ 0, /* Parent */ \
+ 0, /* ACPI Id */ \
+ 1 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package[pid].Slc), \
+ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_16MB, /* Size */ \
+ 16384, /* Num of sets */ \
+ 16, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ { \
+ PPTT_CLUSTER_INIT (pid, 0), \
+ PPTT_CLUSTER_INIT (pid, 1), \
+ PPTT_CLUSTER_INIT (pid, 2), \
+ PPTT_CLUSTER_INIT (pid, 3), \
+ } \
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package[CHIP_COUNT];
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ PPTT_PACKAGE_INIT (0),
+ PPTT_PACKAGE_INIT (1),
+ PPTT_PACKAGE_INIT (2),
+ PPTT_PACKAGE_INIT (3)
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [edk2-platforms][PATCH V2 8/8] Platform/Sgi: ACPI PPTT table for RD-N2 platform
2021-04-28 12:12 [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (6 preceding siblings ...)
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 7/8] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform Pranav Madhu
@ 2021-04-28 12:12 ` Pranav Madhu
2021-05-03 14:25 ` [edk2-devel] [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Thomas Abraham
2021-05-10 9:22 ` Sami Mujawar
9 siblings, 0 replies; 14+ messages in thread
From: Pranav Madhu @ 2021-04-28 12:12 UTC (permalink / raw)
To: devel; +Cc: Ard Biesheuvel, Pierre Gondois, Sami Mujawar
The RD-N2 platform includes sixteen single-thread CPUS. Each of the
CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2
cache. The platform also includes a system level cache of 32MB. Add PPTT
table for RD-N2 platform with this information.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +-
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 164 ++++++++++++++++++++
2 files changed, 166 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index 2ec3e42473a9..c1282a3422ab 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2020, Arm Ltd. All rights reserved.
+# Copyright (c) 2020-2021, Arm Ltd. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -22,6 +22,7 @@
Mcfg.aslc
RdN2/Dsdt.asl
RdN2/Madt.aslc
+ RdN2/Pptt.aslc
Spcr.aslc
Ssdt.asl
SsdtRos.asl
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
new file mode 100644
index 000000000000..1d00110311ab
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
@@ -0,0 +1,164 @@
+/** @file
+* Processor Properties Topology Table (PPTT) for RD-N2 platform
+*
+* This file describes the topological structure of the processor block on the
+* RD-N2 platform in the form as defined by ACPI PPTT table. The RD-N2 platform
+* includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Data
+* cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes
+* system level cache of 32MB.
+*
+* Copyright (c) 2021, ARM Limited. All rights reserved.
+*
+* SPDX-License-Identifier: BSD-2-Clause-Patent
+*
+* @par Specification Reference:
+* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
+**/
+
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+#include "SgiPlatform.h"
+#include "SgiAcpiHeader.h"
+
+#define PPTT_CORE_INIT(pid, cid, cpuid) \
+ { \
+ /* Parameters for CPU Core */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
+ PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid]), /* Parent */ \
+ ((pid << 4) | cid), /* ACPI Id */ \
+ 2 /* Num of private resource */ \
+ ), \
+ \
+ /* Offsets of the private resources */ \
+ { \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].DCache), \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].ICache) \
+ }, \
+ \
+ /* L1 data cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_DATA_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L1 instruction cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package.Cluster[cid].Core[cpuid].L2Cache), \
+ /* Next level of cache */ \
+ SIZE_64KB, /* Size */ \
+ 256, /* Num of sets */ \
+ 4, /* Associativity */ \
+ PPTT_INST_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ \
+ /* L2 cache parameters */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
+ 0, /* Next level of cache */ \
+ SIZE_1MB, /* Size */ \
+ 2048, /* Num of sets */ \
+ 8, /* Associativity */ \
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
+ 64 /* Line size */ \
+ ), \
+ }
+
+#define PPTT_CLUSTER_INIT(pid, cid) \
+ { \
+ /* Parameters for Cluster */ \
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
+ OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \
+ PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
+ Package), /* Parent */ \
+ 0, /* ACPI Id */ \
+ 0 /* Num of private resource */ \
+ ), \
+ \
+ /* Initialize child core */ \
+ { \
+ PPTT_CORE_INIT (pid, cid, 0) \
+ } \
+ }
+
+#pragma pack(1)
+/*
+ * Processor Properties Topology Table
+ */
+typedef struct {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ RD_PPTT_SLC_PACKAGE Package;
+} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+#pragma pack ()
+
+STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ )
+ },
+
+ {
+ EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
+ OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc),
+ PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1),
+
+ OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ Package.Slc),
+
+ EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT (
+ PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
+ 0, /* Next level of cache */
+ SIZE_32MB, /* Size */
+ 32768, /* Num of sets */
+ 16, /* Associativity */
+ PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
+ 64 /* Line size */
+ ),
+
+ {
+ PPTT_CLUSTER_INIT (0, 0),
+ PPTT_CLUSTER_INIT (0, 1),
+ PPTT_CLUSTER_INIT (0, 2),
+ PPTT_CLUSTER_INIT (0, 3),
+ PPTT_CLUSTER_INIT (0, 4),
+ PPTT_CLUSTER_INIT (0, 5),
+ PPTT_CLUSTER_INIT (0, 6),
+ PPTT_CLUSTER_INIT (0, 7),
+ PPTT_CLUSTER_INIT (0, 8),
+ PPTT_CLUSTER_INIT (0, 9),
+ PPTT_CLUSTER_INIT (0, 10),
+ PPTT_CLUSTER_INIT (0, 11),
+ PPTT_CLUSTER_INIT (0, 12),
+ PPTT_CLUSTER_INIT (0, 13),
+ PPTT_CLUSTER_INIT (0, 14),
+ PPTT_CLUSTER_INIT (0, 15)
+ }
+ }
+};
+
+/*
+ * Reference the table being generated to prevent the optimizer from removing
+ * the data structure from the executable
+ */
+VOID* CONST ReferenceAcpiTable = &Pptt;
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [edk2-devel] [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms
2021-04-28 12:12 [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (7 preceding siblings ...)
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 8/8] Platform/Sgi: ACPI PPTT table for RD-N2 platform Pranav Madhu
@ 2021-05-03 14:25 ` Thomas Abraham
2021-05-04 9:44 ` PierreGondois
2021-05-10 9:22 ` Sami Mujawar
9 siblings, 1 reply; 14+ messages in thread
From: Thomas Abraham @ 2021-05-03 14:25 UTC (permalink / raw)
To: devel@edk2.groups.io, Pranav Madhu
Cc: Ard Biesheuvel, Pierre Gondois, Sami Mujawar, nd
On 4/28/21 5:42 PM, Pranav Madhu via groups.io wrote:
> Changes since V1:
> - Rebase the patches on top of latest master branch
> - Addressed comments from Pierre
>
> Processor Properties Topology Table (PPTT) describes the topological
> structure of processors, and their shared resources such as caches.
> This patch series adds PPTT table for Arm's Neoverse Reference Design
> platforms.
>
> The first patch in this series adds helper macros for PPTT table, and
> the subsequent patches in this series adds PPTT table for Neoverse
> Reference Design platforms which is mandatory as per Arm SystemReady SR
> specification.
>
> Link to github branch with the patches in this series -
> https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_pptt
For this series:
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>
>
> Pranav Madhu (8):
> Platform/Sgi: Helper macros for PPTT Table
> Platform/Sgi: ACPI PPTT table for SGI-575 platform
> Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform
> Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip
> Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
> Platform/Sgi: ACPI PPTT Table for RD-V1 platform
> Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform
> Platform/Sgi: ACPI PPTT table for RD-N2 platform
>
> .../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +-
> .../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +-
> .../AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
> .../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +-
> .../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +-
> .../SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 +
> .../SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +-
> Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 160 ++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 230 ++++++++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 175 +++++++++++++
> .../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 192 +++++++++++++++
> Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 163 +++++++++++++
> Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 164 +++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 169 +++++++++++++
> .../ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 161 ++++++++++++
> 15 files changed, 1426 insertions(+), 5 deletions(-)
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
>
> --
> 2.17.1
>
>
>
> -=-=-=-=-=-=
> Groups.io Links: You receive all messages sent to this group.
> View/Reply Online (#74532): https://edk2.groups.io/g/devel/message/74532
> Mute This Topic: https://groups.io/mt/82427819/1785010
> Group Owner: devel+owner@edk2.groups.io
> Unsubscribe: https://edk2.groups.io/g/devel/unsub
> [thomas.abraham@arm.com]
> -=-=-=-=-=-=
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-devel] [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms
2021-05-03 14:25 ` [edk2-devel] [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Thomas Abraham
@ 2021-05-04 9:44 ` PierreGondois
0 siblings, 0 replies; 14+ messages in thread
From: PierreGondois @ 2021-05-04 9:44 UTC (permalink / raw)
To: Thomas Abraham, devel
[-- Attachment #1: Type: text/plain, Size: 109 bytes --]
Hi Pranav,
For the serie aswell:
Reviewed-by: Pierre Gondois <pierre.gondois@arm.com>
Regards,
Pierre
[-- Attachment #2: Type: text/html, Size: 135 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-platforms][PATCH V2 1/8] Platform/Sgi: Helper macros for PPTT Table
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 1/8] Platform/Sgi: Helper macros for PPTT Table Pranav Madhu
@ 2021-05-10 8:43 ` Sami Mujawar
0 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-05-10 8:43 UTC (permalink / raw)
To: Pranav Madhu, devel; +Cc: Ard Biesheuvel, Pierre Gondois
Hi Pranav,
Please find my response inline marked [SAMI].
Regards,
Sami Mujawar
On 28/04/2021 01:12 PM, Pranav Madhu wrote:
> Add helper macros for the creation for PPTT table. These macros help
> with initializing processor hierarchy node structure, cache type
> structure and ID structure.
>
> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
> ---
> Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 160 ++++++++++++++++++++
> 1 file changed, 160 insertions(+)
>
> diff --git a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
> index dcb4e6c77a74..7bb8b6dec6a3 100644
> --- a/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
> +++ b/Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h
> @@ -20,6 +20,131 @@
> #define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('A','R','M',' ')
> #define EFI_ACPI_ARM_CREATOR_REVISION 0x00000099
>
> +#define CORE_COUNT FixedPcdGet32 (PcdCoreCount)
> +#define CLUSTER_COUNT FixedPcdGet32 (PcdClusterCount)
> +
> +#pragma pack(1)
> +// PPTT processor core structure
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Core;
> + UINT32 ResourceOffset[2];
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE DCache;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE ICache;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L2Cache;
> +} RD_PPTT_CORE;
> +
> +// PPTT processor cluster structure
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
> + UINT32 ResourceOffset;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE L3Cache;
> + RD_PPTT_CORE Core[CORE_COUNT];
> +} RD_PPTT_CLUSTER;
> +
> +// PPTT processor cluster structure without cache
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Cluster;
> + RD_PPTT_CORE Core[CORE_COUNT];
> +} RD_PPTT_MINIMAL_CLUSTER;
> +
> +// PPTT processor package structure
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
> + UINT32 ResourceOffset;
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE Slc;
> + RD_PPTT_MINIMAL_CLUSTER Cluster[CLUSTER_COUNT];
> +} RD_PPTT_SLC_PACKAGE;
> +#pragma pack ()
> +
> +//
> +// PPTT processor structure flags for different SoC components as defined in
> +// ACPI 6.3 specification
> +//
> +
> +// Processor structure flags for SoC package
> +#define PPTT_PROCESSOR_PACKAGE_FLAGS \
> + { \
> + EFI_ACPI_6_3_PPTT_PACKAGE_PHYSICAL, \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
> + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
> + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
> + }
> +
> +// Processor structure flags for cluster
> +#define PPTT_PROCESSOR_CLUSTER_FLAGS \
> + { \
> + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
[SAMI] Is there a reason for setting the ID as invalid? In the next CPPC
patch series 'Platform/Sgi: Add CPU container for xxx' the processor
containers "ACPI0010" are described with valid UIDs.
According to the ACPI 6.4 sepcification, Table 5.138: Processor
Hierarchy Node Structure, Field description for 'ACPI Processor ID'
states the following:
"If the processor structure represents a group of associated processors,
the structure might match a processor container in the name space. In
that case this entry
will match the value of the _UID method of the associated processor
container. Where there is a match it must be represented."
So, either this patch series or the next patch series 'Platform/Sgi: Add
CPU container for xxx' will need to address this.
[/SAMI]
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
> + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
> + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
> + }
> +
> +// Processor structure flags for single-thread core
> +#define PPTT_PROCESSOR_CORE_FLAGS \
> + { \
> + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
> + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF \
> + }
> +
> +// Processor structure flags for multi-thread core
> +#define PPTT_PROCESSOR_CORE_THREADED_FLAGS \
> + { \
> + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_INVALID, \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_NOT_THREAD, \
> + EFI_ACPI_6_3_PPTT_NODE_IS_NOT_LEAF, \
> + EFI_ACPI_6_3_PPTT_IMPLEMENTATION_IDENTICAL \
> + }
> +
> +// Processor structure flags for CPU thread
> +#define PPTT_PROCESSOR_THREAD_FLAGS \
> + { \
> + EFI_ACPI_6_3_PPTT_PACKAGE_NOT_PHYSICAL, \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_ID_VALID, \
> + EFI_ACPI_6_3_PPTT_PROCESSOR_IS_THREAD, \
> + EFI_ACPI_6_3_PPTT_NODE_IS_LEAF \
> + }
> +
> +// PPTT cache structure flags as defined in ACPI 6.3 Specification
> +#define PPTT_CACHE_STRUCTURE_FLAGS \
> + { \
> + EFI_ACPI_6_3_PPTT_CACHE_SIZE_VALID, \
> + EFI_ACPI_6_3_PPTT_NUMBER_OF_SETS_VALID, \
> + EFI_ACPI_6_3_PPTT_ASSOCIATIVITY_VALID, \
> + EFI_ACPI_6_3_PPTT_ALLOCATION_TYPE_VALID, \
> + EFI_ACPI_6_3_PPTT_CACHE_TYPE_VALID, \
> + EFI_ACPI_6_3_PPTT_WRITE_POLICY_VALID, \
> + EFI_ACPI_6_3_PPTT_LINE_SIZE_VALID \
> + }
> +
> +// PPTT cache attributes for data cache
> +#define PPTT_DATA_CACHE_ATTR \
> + { \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_DATA, \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
> + }
> +
> +// PPTT cache attributes for instruction cache
> +#define PPTT_INST_CACHE_ATTR \
> + { \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ, \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_INSTRUCTION, \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
> + }
> +
> +// PPTT cache attributes for unified cache
> +#define PPTT_UNIFIED_CACHE_ATTR \
> + { \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE, \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_CACHE_TYPE_UNIFIED, \
> + EFI_ACPI_6_3_CACHE_ATTRIBUTES_WRITE_POLICY_WRITE_BACK \
> + }
> +
> // A macro to initialise the common header part of EFI ACPI tables as defined by
> // EFI_ACPI_DESCRIPTION_HEADER structure.
> #define ARM_ACPI_HEADER(Signature, Type, Revision) { \
> @@ -246,4 +371,39 @@
> TotalCacheLevels, CacheLevel, CacheAssociativity, WritePolicy, CacheLineSize \
> }
>
> +// EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR
> +#define EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT(Length, Flag, Parent, \
> + ACPIProcessorID, NumberOfPrivateResource) \
> + { \
> + EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR, /* Type 0 */ \
> + Length, /* Length */ \
> + { \
> + EFI_ACPI_RESERVED_BYTE, \
> + EFI_ACPI_RESERVED_BYTE, \
> + }, \
> + Flag, /* Processor flags */ \
> + Parent, /* Ref to parent node */ \
> + ACPIProcessorID, /* UID, as per MADT */ \
> + NumberOfPrivateResource /* Resource count */ \
> + }
> +
> +// EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE
> +#define EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT(Flag, NextLevelCache, Size, \
> + NoOfSets, Associativity, Attributes, LineSize) \
> + { \
> + EFI_ACPI_6_3_PPTT_TYPE_CACHE, /* Type 1 */ \
> + sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE), /* Length */ \
> + { \
> + EFI_ACPI_RESERVED_BYTE, \
> + EFI_ACPI_RESERVED_BYTE, \
> + }, \
> + Flag, /* Cache flags */ \
> + NextLevelCache, /* Ref to next level */ \
> + Size, /* Size in bytes */ \
> + NoOfSets, /* Num of sets */ \
> + Associativity, /* Num of ways */ \
> + Attributes, /* Cache attributes */ \
> + LineSize /* Line size in bytes */ \
> + }
> +
> #endif /* __SGI_ACPI_HEADER__ */
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* Re: [edk2-platforms][PATCH V2 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform Pranav Madhu
@ 2021-05-10 8:43 ` Sami Mujawar
0 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-05-10 8:43 UTC (permalink / raw)
To: Pranav Madhu, devel; +Cc: Ard Biesheuvel, Pierre Gondois
Hi Pranav,
Please see my response inline marked [SAMI].
Regards,
Sami Mujawar
On 28/04/2021 01:12 PM, Pranav Madhu wrote:
> From: Pranav Madhu <Pranav.Madhu@arm.com>
>
> The SGI-575 platform includes two clusters with four single-thread CPUs.
> Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache
> and 512KB L2 cache. Each cluster includes a 2MB L3 cache. Add PPTT table
> for SGI-575 platform with this information.
>
> Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
> ---
> Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +-
> Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 161 ++++++++++++++++++++
> 2 files changed, 163 insertions(+), 1 deletion(-)
>
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
> index 2121fd39f2f0..b1ee16e98ea3 100644
> --- a/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
> +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575AcpiTables.inf
> @@ -1,7 +1,7 @@
> ## @file
> # ACPI table data and ASL sources required to boot the platform.
> #
> -# Copyright (c) 2018, ARM Ltd. All rights reserved.
> +# Copyright (c) 2018 - 2021, ARM Ltd. All rights reserved.
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -22,6 +22,7 @@
> Mcfg.aslc
> Sgi575/Dsdt.asl
> Sgi575/Madt.aslc
> + Sgi575/Pptt.aslc
> Spcr.aslc
> Ssdt.asl
>
> diff --git a/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
> new file mode 100644
> index 000000000000..3388a012dd55
> --- /dev/null
> +++ b/Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
> @@ -0,0 +1,161 @@
> +/** @file
> +* Processor Properties Topology Table (PPTT) for SGI-575 platform
> +*
> +* This file describes the topological structure of the processor block on the
> +* SGI-575 platform in the form as defined by ACPI PPTT table. The SGI-575
> +* platform includes two clusters with four single-thread CPUS. Each of the CPUs
> +* include 64KB L1 Data cache, 64KB L1 Instruction cache and 512KB L2 cache.
> +* Each cluster includes a 2MB L3 cache.
> +*
> +* Copyright (c) 2021, ARM Limited. All rights reserved.
> +*
> +* SPDX-License-Identifier: BSD-2-Clause-Patent
> +*
> +* @par Specification Reference:
> +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table
> +**/
> +
> +#include <IndustryStandard/Acpi.h>
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +#include <Library/PcdLib.h>
> +
> +#include "SgiPlatform.h"
> +#include "SgiAcpiHeader.h"
> +
> +#define PPTT_CORE_INIT(pid, cid, cpuid) \
[SAMI] Can you add a doxygen style header describing the parameters. As
it stands the meaning of the macro parameter is not intutive.
I can see the difficulty if PPTT_CORE_INIT() were to be a generic macro,
in which case it may be better to describe the parameters as affinity
levels.
However, in the current case this macro is local, so
- the macro could be modified to suit parameters specific to this file
OR
- Describe the macro parameters as affinity levels and add a Doxygen
function style comment header clarifying the parameter usage.
[/SAMI]
> + { \
> + /* Parameters for CPU Core */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
> + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \
> + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[cid]), /* Parent */ \
> + ((pid << 3) | (cid << 2) | cpuid), /* ACPI Id */ \
> + 2 /* Num of private resource */ \
> + ), \
> + \
> + /* Offsets of the private resources */ \
> + { \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[cid].Core[cpuid].DCache), \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[cid].Core[cpuid].ICache) \
> + }, \
> + \
> + /* L1 data cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[cid].Core[cpuid].L2Cache), \
> + /* Next level of cache */ \
> + SIZE_64KB, /* Size */ \
> + 64, /* Num of sets */ \
> + 16, /* Associativity */ \
> + PPTT_DATA_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + \
> + /* L1 instruction cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[cid].Core[cpuid].L2Cache), \
> + /* Next level of cache */ \
> + SIZE_64KB, /* Size */ \
> + 256, /* Num of sets */ \
> + 4, /* Associativity */ \
> + PPTT_INST_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + \
> + /* L2 cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + 0, /* Next level of cache */ \
> + SIZE_512KB, /* Size */ \
> + 1024, /* Num of sets */ \
> + 8, /* Associativity */ \
> + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + }
> +
> +#define PPTT_CLUSTER_INIT(pid, cid) \
> + { \
> + /* Parameters for Cluster */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \
> + OFFSET_OF (RD_PPTT_CLUSTER, L3Cache), \
> + /* Length */ \
> + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package), /* Parent */ \
> + 0, /* ACPI Id */ \
> + 1 /* Num of private resource */ \
> + ), \
> + \
> + /* Offsets of the private resources */ \
> + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \
> + Package.Cluster[cid].L3Cache), \
> + \
> + /* L3 cache parameters */ \
> + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \
> + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \
> + 0, /* Next level of cache */ \
> + SIZE_2MB, /* Size */ \
> + 2048, /* Num of sets */ \
> + 16, /* Associativity */ \
> + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \
> + 64 /* Line size */ \
> + ), \
> + \
> + /* Initialize child cores */ \
> + { \
> + PPTT_CORE_INIT (pid, cid, 0), \
> + PPTT_CORE_INIT (pid, cid, 1), \
> + PPTT_CORE_INIT (pid, cid, 2), \
> + PPTT_CORE_INIT (pid, cid, 3) \
> + } \
> + }
> +
> +#pragma pack(1)
> +typedef struct {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR Package;
> + RD_PPTT_CLUSTER Cluster[CLUSTER_COUNT];
> +} SGI575_PPTT_PACKAGE;
> +
> +/*
> + * Processor Properties Topology Table
> + */
> +typedef struct {
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
> + SGI575_PPTT_PACKAGE Package;
> +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
> +#pragma pack ()
> +
> +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = {
> + {
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
> + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
> + )
> + },
> +
> + {
> + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT (
> + OFFSET_OF (SGI575_PPTT_PACKAGE, Cluster[0]),
> + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 0
> + ),
> + {
> + PPTT_CLUSTER_INIT (0, 0),
> + PPTT_CLUSTER_INIT (0, 1)
> + }
> + }
> +};
> +
> +/*
> + * Reference the table being generated to prevent the optimizer from removing
> + * the data structure from the executable
> + */
> +VOID* CONST ReferenceAcpiTable = &Pptt;
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms
2021-04-28 12:12 [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
` (8 preceding siblings ...)
2021-05-03 14:25 ` [edk2-devel] [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Thomas Abraham
@ 2021-05-10 9:22 ` Sami Mujawar
9 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-05-10 9:22 UTC (permalink / raw)
To: Pranav Madhu, devel; +Cc: Ard Biesheuvel, Pierre Gondois, nd
Hi Pranav,
Is it possible to send the PPTT table dump using ACPIview for these
platforms, please?
Shell> acpiview -s PPTT
Regards,
Sami Mujawar
On 28/04/2021 01:12 PM, Pranav Madhu wrote:
> Changes since V1:
> - Rebase the patches on top of latest master branch
> - Addressed comments from Pierre
>
> Processor Properties Topology Table (PPTT) describes the topological
> structure of processors, and their shared resources such as caches.
> This patch series adds PPTT table for Arm's Neoverse Reference Design
> platforms.
>
> The first patch in this series adds helper macros for PPTT table, and
> the subsequent patches in this series adds PPTT table for Neoverse
> Reference Design platforms which is mandatory as per Arm SystemReady SR
> specification.
>
> Link to github branch with the patches in this series -
> https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_pptt
>
> Pranav Madhu (8):
> Platform/Sgi: Helper macros for PPTT Table
> Platform/Sgi: ACPI PPTT table for SGI-575 platform
> Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform
> Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip
> Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform
> Platform/Sgi: ACPI PPTT Table for RD-V1 platform
> Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform
> Platform/Sgi: ACPI PPTT table for RD-N2 platform
>
> .../SgiPkg/AcpiTables/RdE1EdgeAcpiTables.inf | 3 +-
> .../SgiPkg/AcpiTables/RdN1EdgeAcpiTables.inf | 3 +-
> .../AcpiTables/RdN1EdgeX2AcpiTables.inf | 1 +
> .../ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +-
> .../ARM/SgiPkg/AcpiTables/RdV1AcpiTables.inf | 3 +-
> .../SgiPkg/AcpiTables/RdV1McAcpiTables.inf | 1 +
> .../SgiPkg/AcpiTables/Sgi575AcpiTables.inf | 3 +-
> Platform/ARM/SgiPkg/Include/SgiAcpiHeader.h | 160 ++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc | 230 ++++++++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc | 175 +++++++++++++
> .../SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc | 192 +++++++++++++++
> Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 163 +++++++++++++
> Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc | 164 +++++++++++++
> .../ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 169 +++++++++++++
> .../ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc | 161 ++++++++++++
> 15 files changed, 1426 insertions(+), 5 deletions(-)
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdE1Edge/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1Edge/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN1EdgeX2/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
> create mode 100644 Platform/ARM/SgiPkg/AcpiTables/Sgi575/Pptt.aslc
>
^ permalink raw reply [flat|nested] 14+ messages in thread
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2021-04-28 12:12 [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 1/8] Platform/Sgi: Helper macros for PPTT Table Pranav Madhu
2021-05-10 8:43 ` Sami Mujawar
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 2/8] Platform/Sgi: ACPI PPTT table for SGI-575 platform Pranav Madhu
2021-05-10 8:43 ` Sami Mujawar
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 3/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge platform Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 4/8] Platform/Sgi: ACPI PPTT table for RD-N1-Edge dual-chip Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 5/8] Platform/Sgi: ACPI PPTT table for RD-E1-Edge platform Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 6/8] Platform/Sgi: ACPI PPTT Table for RD-V1 platform Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 7/8] Platform/Sgi: ACPI PPTT Table for RD-V1 quad-chip platform Pranav Madhu
2021-04-28 12:12 ` [edk2-platforms][PATCH V2 8/8] Platform/Sgi: ACPI PPTT table for RD-N2 platform Pranav Madhu
2021-05-03 14:25 ` [edk2-devel] [edk2-platforms][PATCH V2 0/8] Platform/Sgi: Add PPTT table for Neoverse Reference Design platforms Thomas Abraham
2021-05-04 9:44 ` PierreGondois
2021-05-10 9:22 ` Sami Mujawar
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