From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx6-phx2.redhat.com (mx6-phx2.redhat.com [209.132.183.39]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4925681E6D for ; Thu, 10 Nov 2016 08:39:20 -0800 (PST) Received: from zmail13.collab.prod.int.phx2.redhat.com (zmail13.collab.prod.int.phx2.redhat.com [10.5.83.15]) by mx6-phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uAAGdM3U025723; Thu, 10 Nov 2016 11:39:22 -0500 Date: Thu, 10 Nov 2016 11:39:21 -0500 (EST) From: Paolo Bonzini To: Laszlo Ersek Cc: Jiewen Yao , Feng Tian , edk2-devel@ml01.01.org, Michael D Kinney , Jeff Fan , Star Zeng Message-ID: <1042282326.11988922.1478795961783.JavaMail.zimbra@redhat.com> In-Reply-To: <305270ae-51ee-07ba-fb6b-1d66cc5ba8fc@redhat.com> References: <1478251854-14660-1-git-send-email-jiewen.yao@intel.com> <74D8A39837DF1E4DA445A8C0B3885C50386C0CB8@shsmsx102.ccr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C50386CE375@shsmsx102.ccr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C50386CE6AA@shsmsx102.ccr.corp.intel.com> <2492b3b2-1eb7-2563-642f-9a888d9e7fbd@redhat.com> <305270ae-51ee-07ba-fb6b-1d66cc5ba8fc@redhat.com> MIME-Version: 1.0 X-Originating-IP: [10.4.164.1, 10.5.100.50] X-Mailer: Zimbra 8.0.6_GA_5922 (ZimbraWebClient - FF49 (Linux)/8.0.6_GA_5922) Thread-Topic: Enable SMM page level protection. Thread-Index: SjVwoM6GsfW5oWRJOw+dBIlGAlsiXQ== Subject: Re: [PATCH V2 0/6] Enable SMM page level protection. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 10 Nov 2016 16:39:20 -0000 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit > And, in my recent KVM / QEMU usage instructions for Jiewen: > > https://www.mail-archive.com/edk2-devel@lists.01.org/msg19446.html > > I provided the following settings: > > > # Settings for Ia32 only: > > [...] > > QEMU_COMMAND="qemu-system-i386 -cpu coreduo,-nx" > > > > # Settings for Ia32X64 only: > > [...] > > QEMU_COMMAND=qemu-system-x86_64 > > I guess the "-nx" bit can be left off with TCG, but AFAIR it is required > for KVM. Oh right now I remember. The same problem exists: EFER is not saved in the 32-bit state save map. AFAIK all processors with XD also have long mode. That said, qemu-system-x86_64 and no -cpu option should work even with Ia32 PEI/DXE/SMM and no -cpu option. In that case you could use XD. Now if only Intel made the *full* format of the state save map public, we could emulate everything more accurately... I'm told it's in the BIOS writers guide. Paolo