From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.50637.1585576556948966802 for ; Mon, 30 Mar 2020 06:55:57 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: liming.gao@intel.com) IronPort-SDR: fMMLm3Zmosd0O5v1hWSqkxYUynqrhyBKUHq7mUaJxMGmQHJP+epO2bkhlUcfTt0DWlD9ivQwXq cj3vaMfvv9sg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2020 06:55:49 -0700 IronPort-SDR: xWi8G5+XvWWlxbU3RbFfRzaUCKq9+hL7yd++WtszfLCFqStB7A6rx3e9AOA+ioU93MsmXLeUsQ aGVfRbsbkeMw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,324,1580803200"; d="scan'208";a="248705880" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga003.jf.intel.com with ESMTP; 30 Mar 2020 06:55:49 -0700 Received: from shsmsx602.ccr.corp.intel.com (10.109.6.142) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 30 Mar 2020 06:55:48 -0700 Received: from shsmsx606.ccr.corp.intel.com (10.109.6.216) by SHSMSX602.ccr.corp.intel.com (10.109.6.142) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 30 Mar 2020 21:55:46 +0800 Received: from shsmsx606.ccr.corp.intel.com ([10.109.6.216]) by SHSMSX606.ccr.corp.intel.com ([10.109.6.216]) with mapi id 15.01.1713.004; Mon, 30 Mar 2020 21:55:46 +0800 From: "Liming Gao" To: "Javeed, Ashraf" , "devel@edk2.groups.io" CC: "Kinney, Michael D" Subject: Re: [PATCH V2 1/2] MdePkg-IndustryStandard: CXL 1.1 Base Specification registers Thread-Topic: [PATCH V2 1/2] MdePkg-IndustryStandard: CXL 1.1 Base Specification registers Thread-Index: AQHV/6NCHEZPwKhbD0CX1F/TjtlhM6hhNjZg Date: Mon, 30 Mar 2020 13:55:46 +0000 Message-ID: <1067906f96234c62bb2b86852cbd90e4@intel.com> References: <20200321170726.9760-1-ashraf.javeed@intel.com> <20200321170726.9760-2-ashraf.javeed@intel.com> In-Reply-To: <20200321170726.9760-2-ashraf.javeed@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.2.0.6 dlp-product: dlpe-windows dlp-reaction: no-action x-originating-ip: [10.239.127.36] MIME-Version: 1.0 Return-Path: liming.gao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Ashraf: Please include PciExpress50.h in Pci.h, and remove other PciExpressionXX.= h, because PciExpress50.h includes all version PciExpress. Thanks Liming > -----Original Message----- > From: Javeed, Ashraf > Sent: Sunday, March 22, 2020 1:07 AM > To: devel@edk2.groups.io > Cc: Kinney, Michael D ; Gao, Liming > Subject: [PATCH V2 1/2] MdePkg-IndustryStandard: CXL 1.1 Base Specificati= on registers >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2611 >=20 > Register definitions from chapter 7 of CXL Base Specification Rev.1.1 > are ported into the new Cxl11.h. > The CXL Flex Bus registers are based on the PCIe Extended Capability > DVSEC structure headers, hence the Pci.h has to upgraded. >=20 > Signed-off-by: Ashraf Javeed > Cc: Michael D Kinney > Cc: Liming Gao > --- > MdePkg/Include/IndustryStandard/Cxl11.h | 526 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++ > MdePkg/Include/IndustryStandard/Pci.h | 1 + > 2 files changed, 527 insertions(+) >=20 > diff --git a/MdePkg/Include/IndustryStandard/Cxl11.h b/MdePkg/Include/Ind= ustryStandard/Cxl11.h > new file mode 100644 > index 0000000000..65c900142e > --- /dev/null > +++ b/MdePkg/Include/IndustryStandard/Cxl11.h > @@ -0,0 +1,526 @@ > +/** @file > + CXL 1.1 Register definitions > + > + This file contains the register definitions based on the Compute Expre= ss Link > + (CXL) Base Specification Revision 1.1. > + > +Copyright (c) 2020, Intel Corporation. All rights reserved.
> +SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef _CXL11_H_ > +#define _CXL11_H_ > + > +#include > + > +// > +// Ensure proper structure formats > +// > +#pragma pack(1) > + > +/// > +/// The PCIe DVSEC for Flex Bus device > +/// > +typedef union { > + struct { > + UINT16 CacheCapable : 1; // = bit 0 > + UINT16 IoCapable : 1; // = bit 1 > + UINT16 MemCapable : 1; // = bit 2 > + UINT16 MemHwInitMode : 1; // = bit 3 > + UINT16 HdmCount : 2; // = bit 4..5 > + UINT16 Reserved1 : 8; // = bit 6..13 > + UINT16 ViralCapable : 1; // = bit 14 > + UINT16 Reserved2 : 1; // = bit 15 > + }Bits; > + UINT16 Uint16; > +} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY; > + > +typedef union { > + struct { > + UINT16 CacheEnable : 1; // = bit 0 > + UINT16 IoEnable : 1; // = bit 1 > + UINT16 MemEnable : 1; // = bit 2 > + UINT16 CacheSfCoverage : 5; // = bit 3..7 > + UINT16 CacheSfGranularity : 3; // = bit 8..10 > + UINT16 CacheCleanEviction : 1; // = bit 11 > + UINT16 Reserved1 : 2; // = bit 12..13 > + UINT16 ViralEnable : 1; // = bit 14 > + UINT16 Reserved2 : 1; // = bit 15 > + }Bits; > + UINT16 Uint16; > +} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL; > + > +typedef union { > + struct { > + UINT16 Reserved1 : 14; //= bit 0..13 > + UINT16 ViralStatus : 1; //= bit 14 > + UINT16 Reserved2 : 1; //= bit 15 > + }Bits; > + UINT16 Uint16; > +} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS; > + > +typedef union { > + struct { > + UINT16 Reserved1 : 1; //= bit 0 > + UINT16 Reserved2 : 1; //= bit 1 > + UINT16 Reserved3 : 1; //= bit 2 > + UINT16 Reserved4 : 13; //= bit 3..15 > + }Bits; > + UINT16 Uint16; > +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2; > + > +typedef union { > + struct { > + UINT16 Reserved1 : 1; //= bit 0 > + UINT16 Reserved2 : 1; //= bit 1 > + UINT16 Reserved3 : 14; //= bit 2..15 > + }Bits; > + UINT16 Uint16; > +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2; > + > +typedef union { > + struct { > + UINT16 ConfigLock : 1; //= bit 0 > + UINT16 Reserved1 : 15; //= bit 1..15 > + }Bits; > + UINT16 Uint16; > +} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK; > + > +typedef union { > + struct { > + UINT32 MemorySizeHigh : 32; //= bit 0..31 > + }Bits; > + UINT32 Uint32; > +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH; > + > +typedef union { > + struct { > + UINT32 MemoryInfoValid : 1; //= bit 0 > + UINT32 MemoryActive : 1; //= bit 1 > + UINT32 MediaType : 3; //= bit 2..4 > + UINT32 MemoryClass : 3; //= bit 5..7 > + UINT32 DesiredInterleave : 3; //= bit 8..10 > + UINT32 Reserved : 17; //= bit 11..27 > + UINT32 MemorySizeLow : 4; //= bit 28..31 > + }Bits; > + UINT32 Uint32; > +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW; > + > +typedef union { > + struct { > + UINT32 MemoryBaseHigh : 32; //= bit 0..31 > + }Bits; > + UINT32 Uint32; > +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH; > + > +typedef union { > + struct { > + UINT32 Reserved : 28; //= bit 0..27 > + UINT32 MemoryBaseLow : 4; //= bit 28..31 > + }Bits; > + UINT32 Uint32; > +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW; > + > + > +typedef union { > + struct { > + UINT32 MemorySizeHigh : 32; //= bit 0..31 > + }Bits; > + UINT32 Uint32; > +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH; > + > +typedef union { > + struct { > + UINT32 MemoryInfoValid : 1; //= bit 0 > + UINT32 MemoryActive : 1; //= bit 1 > + UINT32 MediaType : 3; //= bit 2..4 > + UINT32 MemoryClass : 3; //= bit 5..7 > + UINT32 DesiredInterleave : 3; //= bit 8..10 > + UINT32 Reserved : 17; //= bit 11..27 > + UINT32 MemorySizeLow : 4; //= bit 28..31 > + }Bits; > + UINT32 Uint32; > +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW; > + > +typedef union { > + struct { > + UINT32 MemoryBaseHigh : 32; //= bit 0..31 > + }Bits; > + UINT32 Uint32; > +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH; > + > +typedef union { > + struct { > + UINT32 Reserved : 28; //= bit 0..27 > + UINT32 MemoryBaseLow : 4; //= bit 28..31 > + }Bits; > + UINT32 Uint32; > +} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW; > + > +typedef struct { > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; = // offset 0 > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 Designat= edVendorSpecificHeader1; // offset 4 > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 Designat= edVendorSpecificHeader2; // offset 8 > + CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DvsecFle= xBusDeviceCapability; // offset 10 > + CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DvsecFle= xBusDeviceControl; // offset 12 > + CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DvsecFle= xBusDeviceStatus; // offset 14 > + CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DvsecFle= xBusDeviceControl2; // offset 16 > + CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DvsecFle= xBusDeviceStatus2; // offset 18 > + CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DvsecFle= xBusDeviceLock; // offset 20 > + UINT16 Reserved= ; // offset 22 > + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DvsecFle= xBusDeviceRange1SizeHigh; // offset 24 > + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DvsecFle= xBusDeviceRange1SizeLow; // offset 28 > + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DvsecFle= xBusDeviceRange1BaseHigh; // offset 32 > + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DvsecFle= xBusDeviceRange1BaseLow; // offset 36 > + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DvsecFle= xBusDeviceRange2SizeHigh; // offset 40 > + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DvsecFle= xBusDeviceRange2SizeLow; // offset 44 > + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DvsecFle= xBusDeviceRange2BaseHigh; // offset 48 > + CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DvsecFle= xBusDeviceRange2BaseLow; // offset 52 > +} CXL_1_1_DVSEC_FLEX_BUS_DEVICE; > + > +/// > +/// PCIe DVSEC for FLex Bus Port > +/// > +typedef union { > + struct { > + UINT16 CacheCapable : 1; //= bit 0 > + UINT16 IoCapable : 1; //= bit 1 > + UINT16 MemCapable : 1; //= bit 2 > + UINT16 Reserved : 13; //= bit 3..15 > + }Bits; > + UINT16 Uint16; > +} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY; > + > +typedef union { > + struct { > + UINT16 CacheEnable : 1; // = bit 0 > + UINT16 IoEnable : 1; // = bit 1 > + UINT16 MemEnable : 1; // = bit 2 > + UINT16 CxlSyncBypassEnable : 1; // = bit 3 > + UINT16 DriftBufferEnable : 1; // = bit 4 > + UINT16 Reserved : 3; // = bit 5..7 > + UINT16 Retimer1Present : 1; // = bit 8 > + UINT16 Retimer2Present : 1; // = bit 9 > + UINT16 Reserved2 : 6; // = bit 10..15 > + }Bits; > + UINT16 Uint16; > +} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL; > + > +typedef union { > + struct { > + UINT16 CacheEnable : 1; // = bit 0 > + UINT16 IoEnable : 1; // = bit 1 > + UINT16 MemEnable : 1; // = bit 2 > + UINT16 CxlSyncBypassEnable : 1; // = bit 3 > + UINT16 DriftBufferEnable : 1; // = bit 4 > + UINT16 Reserved : 3; // = bit 5..7 > + UINT16 CxlCorrectableProtocolIdFramingError : 1; // = bit 8 > + UINT16 CxlUncorrectableProtocolIdFramingError : 1; // = bit 9 > + UINT16 CxlUnexpectedProtocolIdDropped : 1; // = bit 10 > + UINT16 Reserved2 : 5; // = bit 11..15 > + }Bits; > + UINT16 Uint16; > +} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS; > + > +typedef struct { > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; = // offset 0 > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 Designat= edVendorSpecificHeader1; // offset 4 > + PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 Designat= edVendorSpecificHeader2; // offset 8 > + CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY DvsecFle= xBusPortCapability; // offset 10 > + CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL DvsecFle= xBusPortControl; // offset 12 > + CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS DvsecFle= xBusPortStatus; // offset 14 > +} CXL_1_1_DVSEC_FLEX_BUS_PORT; > + > +/// > +/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers > +/// > + > +/// The CXL.Cache and CXL.Memory Architectural register definitions > +/// Based on section 7.2.2 of CXL Base Specification Rev. 1.1 > +///@{ > + > +#define CXL_CAPABILITY_HEADER_OFFSET 0 > +typedef union { > + struct { > + UINT32 CxlCapabilityId : 16; //= bit 0..15 > + UINT32 CxlCapabilityVersion : 4; //= bit 16..19 > + UINT32 CxlCacheMemVersion : 4; //= bit 20..23 > + UINT32 ArraySize : 8; //= bit 24..31 > + } Bits; > + UINT32 Uint32; > +} CXL_CAPABILITY_HEADER; > + > +#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4 > +typedef union { > + struct { > + UINT32 CxlCapabilityId : 16; //= bit 0..15 > + UINT32 CxlCapabilityVersion : 4; //= bit 16..19 > + UINT32 CxlRasCapabilityPointer : 12; //= bit 20..31 > + } Bits; > + UINT32 Uint32; > +} CXL_RAS_CAPABILITY_HEADER; > + > +#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8 > +typedef union { > + struct { > + UINT32 CxlCapabilityId : 16; //= bit 0..15 > + UINT32 CxlCapabilityVersion : 4; //= bit 16..19 > + UINT32 CxlSecurityCapabilityPointer : 12; //= bit 20..31 > + } Bits; > + UINT32 Uint32; > +} CXL_SECURITY_CAPABILITY_HEADER; > + > +#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC > +typedef union { > + struct { > + UINT32 CxlCapabilityId : 16; //= bit 0..15 > + UINT32 CxlCapabilityVersion : 4; //= bit 16..19 > + UINT32 CxlLinkCapabilityPointer : 12; //= bit 20..31 > + } Bits; > + UINT32 Uint32; > +} CXL_LINK_CAPABILITY_HEADER; > + > +typedef union { > + struct { > + UINT32 CacheDataParity : 1; //= bit 0..0 > + UINT32 CacheAddressParity : 1; //= bit 1..1 > + UINT32 CacheByteEnableParity : 1; //= bit 2..2 > + UINT32 CacheDataEcc : 1; //= bit 3..3 > + UINT32 MemDataParity : 1; //= bit 4..4 > + UINT32 MemAddressParity : 1; //= bit 5..5 > + UINT32 MemByteEnableParity : 1; //= bit 6..6 > + UINT32 MemDataEcc : 1; //= bit 7..7 > + UINT32 ReInitThreshold : 1; //= bit 8..8 > + UINT32 RsvdEncodingViolation : 1; //= bit 9..9 > + UINT32 PoisonReceived : 1; //= bit 10..10 > + UINT32 ReceiverOverflow : 1; //= bit 11..11 > + UINT32 Reserved : 20; //= bit 12..31 > + } Bits; > + UINT32 Uint32; > +} CXL_1_1_UNCORRECTABLE_ERROR_STATUS; > + > +typedef union { > + struct { > + UINT32 CacheDataParityMask : 1; //= bit 0..0 > + UINT32 CacheAddressParityMask : 1; //= bit 1..1 > + UINT32 CacheByteEnableParityMask : 1; //= bit 2..2 > + UINT32 CacheDataEccMask : 1; //= bit 3..3 > + UINT32 MemDataParityMask : 1; //= bit 4..4 > + UINT32 MemAddressParityMask : 1; //= bit 5..5 > + UINT32 MemByteEnableParityMask : 1; //= bit 6..6 > + UINT32 MemDataEccMask : 1; //= bit 7..7 > + UINT32 ReInitThresholdMask : 1; //= bit 8..8 > + UINT32 RsvdEncodingViolationMask : 1; //= bit 9..9 > + UINT32 PoisonReceivedMask : 1; //= bit 10..10 > + UINT32 ReceiverOverflowMask : 1; //= bit 11..11 > + UINT32 Reserved : 20; //= bit 12..31 > + } Bits; > + UINT32 Uint32; > +} CXL_1_1_UNCORRECTABLE_ERROR_MASK; > + > +typedef union { > + struct { > + UINT32 CacheDataParitySeverity : 1; //= bit 0..0 > + UINT32 CacheAddressParitySeverity : 1; //= bit 1..1 > + UINT32 CacheByteEnableParitySeverity : 1; //= bit 2..2 > + UINT32 CacheDataEccSeverity : 1; //= bit 3..3 > + UINT32 MemDataParitySeverity : 1; //= bit 4..4 > + UINT32 MemAddressParitySeverity : 1; //= bit 5..5 > + UINT32 MemByteEnableParitySeverity : 1; //= bit 6..6 > + UINT32 MemDataEccSeverity : 1; //= bit 7..7 > + UINT32 ReInitThresholdSeverity : 1; //= bit 8..8 > + UINT32 RsvdEncodingViolationSeverity : 1; //= bit 9..9 > + UINT32 PoisonReceivedSeverity : 1; //= bit 10..10 > + UINT32 ReceiverOverflowSeverity : 1; //= bit 11..11 > + UINT32 Reserved : 20; //= bit 12..31 > + } Bits; > + UINT32 Uint32; > +} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY; > + > +typedef union { > + struct { > + UINT32 CacheDataEcc : 1; //= bit 0..0 > + UINT32 MemoryDataEcc : 1; //= bit 1..1 > + UINT32 CrcThreshold : 1; //= bit 2..2 > + UINT32 RetryThreshold : 1; //= bit 3..3 > + UINT32 CachePoisonReceived : 1; //= bit 4..4 > + UINT32 MemoryPoisonReceived : 1; //= bit 5..5 > + UINT32 PhysicalLayerError : 1; //= bit 6..6 > + UINT32 Reserved : 25; //= bit 7..31 > + } Bits; > + UINT32 Uint32; > +} CXL_CORRECTABLE_ERROR_STATUS; > + > +typedef union { > + struct { > + UINT32 CacheDataEccMask : 1; //= bit 0..0 > + UINT32 MemoryDataEccMask : 1; //= bit 1..1 > + UINT32 CrcThresholdMask : 1; //= bit 2..2 > + UINT32 RetryThresholdMask : 1; //= bit 3..3 > + UINT32 CachePoisonReceivedMask : 1; //= bit 4..4 > + UINT32 MemoryPoisonReceivedMask : 1; //= bit 5..5 > + UINT32 PhysicalLayerErrorMask : 1; //= bit 6..6 > + UINT32 Reserved : 25; //= bit 7..31 > + } Bits; > + UINT32 Uint32; > +} CXL_CORRECTABLE_ERROR_MASK; > + > +typedef union { > + struct { > + UINT32 FirstErrorPointer : 4; //= bit 0..3 > + UINT32 Reserved1 : 5; //= bit 4..8 > + UINT32 MultipleHeaderRecordingCapability : 1; //= bit 9..9 > + UINT32 Reserved2 : 3; //= bit 10..12 > + UINT32 PoisonEnabled : 1; //= bit 13..13 > + UINT32 Reserved3 : 18; //= bit 14..31 > + } Bits; > + UINT32 Uint32; > +} CXL_ERROR_CAPABILITIES_AND_CONTROL; > + > +typedef struct { > + CXL_1_1_UNCORRECTABLE_ERROR_STATUS HeaderLo= g[16]; > +} CXL_HEADER_LOG; > + > +typedef struct { > + CXL_1_1_UNCORRECTABLE_ERROR_STATUS Uncorrec= tableErrorStatus; // offset 0 > + CXL_1_1_UNCORRECTABLE_ERROR_MASK Uncorrec= tableErrorMask; // offset 4 > + CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY Uncorrec= tableErrorSeverity; // offset 8 > + CXL_CORRECTABLE_ERROR_STATUS Correcta= bleErrorStatus; // offset 12 > + CXL_CORRECTABLE_ERROR_MASK Correcta= bleErrorMask; // offset 16 > + CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCap= abilitiesAndControl; // offset 20 > + CXL_HEADER_LOG HeaderLo= g; // offset 24 > +} CXL_1_1_RAS_CAPABILITY_STRUCTURE; > + > +typedef union { > + struct { > + UINT32 DeviceTrustLevel : 2; //= bit 0..1 > + UINT32 Reserved : 30; //= bit 2..31 > + } Bits; > + UINT32 Uint32; > +} CXL_1_1_SECURITY_POLICY; > + > +typedef struct { > + CXL_1_1_SECURITY_POLICY Security= Policy; > +} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE; > + > +typedef union { > + struct { > + UINT64 CxlLinkVersionSupported : 4; //= bit 0..3 > + UINT64 CxlLinkVersionReceived : 4; //= bit 4..7 > + UINT64 LlrWrapValueSupported : 8; //= bit 8..15 > + UINT64 LlrWrapValueReceived : 8; //= bit 16..23 > + UINT64 NumRetryReceived : 5; //= bit 24..28 > + UINT64 NumPhyReinitReceived : 5; //= bit 29..33 > + UINT64 WrPtrReceived : 8; //= bit 34..41 > + UINT64 EchoEseqReceived : 8; //= bit 42..49 > + UINT64 NumFreeBufReceived : 8; //= bit 50..57 > + UINT64 Reserved : 6; //= bit 58..63 > + } Bits; > + UINT64 Uint64; > +} CXL_LINK_LAYER_CAPABILITY; > + > +typedef union { > + struct { > + UINT16 LlReset : 1; //= bit 0..0 > + UINT16 LlInitStall : 1; //= bit 1..1 > + UINT16 LlCrdStall : 1; //= bit 2..2 > + UINT16 InitState : 2; //= bit 3..4 > + UINT16 LlRetryBufferConsumed : 8; //= bit 5..12 > + UINT16 Reserved : 3; //= bit 13..15 > + } Bits; > + UINT16 Uint16; > +} CXL_LINK_LAYER_CONTROL_AND_STATUS; > + > +typedef union { > + struct { > + UINT64 CacheReqCredits : 10; //= bit 0..9 > + UINT64 CacheRspCredits : 10; //= bit 10..19 > + UINT64 CacheDataCredits : 10; //= bit 20..29 > + UINT64 MemReqRspCredits : 10; //= bit 30..39 > + UINT64 MemDataCredits : 10; //= bit 40..49 > + } Bits; > + UINT64 Uint64; > +} CXL_LINK_LAYER_RX_CREDIT_CONTROL; > + > +typedef union { > + struct { > + UINT64 CacheReqCredits : 10; //= bit 0..9 > + UINT64 CacheRspCredits : 10; //= bit 10..19 > + UINT64 CacheDataCredits : 10; //= bit 20..29 > + UINT64 MemReqRspCredits : 10; //= bit 30..39 > + UINT64 MemDataCredits : 10; //= bit 40..49 > + } Bits; > + UINT64 Uint64; > +} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS; > + > +typedef union { > + struct { > + UINT64 CacheReqCredits : 10; //= bit 0..9 > + UINT64 CacheRspCredits : 10; //= bit 10..19 > + UINT64 CacheDataCredits : 10; //= bit 20..29 > + UINT64 MemReqRspCredits : 10; //= bit 30..39 > + UINT64 MemDataCredits : 10; //= bit 40..49 > + } Bits; > + UINT64 Uint64; > +} CXL_LINK_LAYER_TX_CREDIT_STATUS; > + > +typedef union { > + struct { > + UINT32 AckForceThreshold : 8; //= bit 0..7 > + UINT32 AckFLushRetimer : 10; //= bit 8..17 > + } Bits; > + UINT32 Uint32; > +} CXL_LINK_LAYER_ACK_TIMER_CONTROL; > + > +typedef union { > + struct { > + UINT32 MdhDisable : 1; //= bit 0..0 > + UINT32 Reserved : 31; //= bit 1..31 > + } Bits; > + UINT32 Uint32; > +} CXL_LINK_LAYER_DEFEATURE; > + > +typedef struct { > + CXL_LINK_LAYER_CAPABILITY LinkLaye= rCapability; // offset 0 > + CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLaye= rControlStatus; // offset 8 > + CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLaye= rRxCreditControl; // offset 10 > + CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLaye= rRxCreditReturnStatus; // offset 18 > + CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLaye= rTxCreditStatus; // offset 26 > + CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLaye= rAckTimerControl; // offset 34 > + CXL_LINK_LAYER_DEFEATURE LinkLaye= rDefeature; // offset 38 > +} CXL_1_1_LINK_CAPABILITY_STRUCTURE; > + > +#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180 > +typedef union { > + struct { > + UINT32 Reserved1 : 4; //= bit 0..3 > + UINT32 WeightedRoundRobinArbitrationWeight : 4; //= bit 4..7 > + UINT32 Reserved2 : 24; //= bit 8..31 > + } Bits; > + UINT32 Uint32; > +} CXL_IO_ARBITRATION_CONTROL; > + > +#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0 > +typedef union { > + struct { > + UINT32 Reserved1 : 4; //= bit 0..3 > + UINT32 WeightedRoundRobinArbitrationWeight : 4; //= bit 4..7 > + UINT32 Reserved2 : 24; //= bit 8..31 > + } Bits; > + UINT32 Uint32; > +} CXL_CACHE_MEMORY_ARBITRATION_CONTROL; > +///@} > + > +typedef union { > + struct { > + UINT64 RcrbEnable : 1; //= bit 0..0 > + UINT64 Reserved : 12; //= bit 1..12 > + UINT64 RcrbBaseAddress : 51; //= bit 13..63 > + } Bits; > + UINT64 Uint64; > +} CXL_RCRB_BASE; > + > +#pragma pack() > + > +#endif > diff --git a/MdePkg/Include/IndustryStandard/Pci.h b/MdePkg/Include/Indus= tryStandard/Pci.h > index 8ed96b992a..86da00d4ed 100644 > --- a/MdePkg/Include/IndustryStandard/Pci.h > +++ b/MdePkg/Include/IndustryStandard/Pci.h > @@ -12,6 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #include > #include > #include > +#include > #include >=20 > #endif > -- > 2.21.0.windows.1