From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by mx.groups.io with SMTP id smtpd.web10.9589.1645706023543032267 for ; Thu, 24 Feb 2022 04:33:43 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=JmIDQEqf; spf=pass (domain: quicinc.com, ip: 199.106.114.38, mailfrom: quic_tpilar@quicinc.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1645706023; x=1677242023; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=CaNqbc60bPz4JZNzVvAD62kw2CY4EF0wR0YeGM5SD9w=; b=JmIDQEqf+mEkfBsKEMYPLtZEAz4mmZllED2+P+khqM68URO3lVWku9Q4 kn84iEOyHbeaxK4XdG1ZVxRUhkFHtkD41h2sedrvkqB5lQ/BMEgGcoPAj DaXaDg3iCUaiKtfLYuxzIetm5Qs/HpvP594KnnAg+iluOfQpZAMVus8F6 M=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 24 Feb 2022 04:33:42 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Feb 2022 04:33:42 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Thu, 24 Feb 2022 04:33:42 -0800 Received: from [10.111.143.207] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Thu, 24 Feb 2022 04:33:40 -0800 Message-ID: <10febc7f-62d5-f6fe-0078-ca971274742b@quicinc.com> Date: Thu, 24 Feb 2022 12:33:38 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH] MdeModulePkg: Correct high-memory use in NvmExpressDxe To: Ard Biesheuvel CC: edk2-devel-groups-io , Ray Ni , Ard Biesheuvel , Leif Lindholm References: <20220224114744.1966974-1-quic_tpilar@quicinc.com> From: "Tomas Pilar (tpilar)" In-Reply-To: Return-Path: quic_tpilar@quicinc.com X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit On 24/02/2022 12:09, Ard Biesheuvel wrote: > On Thu, 24 Feb 2022 at 12:58, Ard Biesheuvel wrote: >> On Thu, 24 Feb 2022 at 12:48, Tomas Pilar wrote: >>> Delay and move the allocation and mapping of memory that backs the DMA >>> engine in NvmExpress devices to NvmeInit() to ensure that >>> the allocation only happens after the >>> EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute is set >>> on the PciIo controller. >>> >>> This ensures that the DMA-backing memory is not forcibly allocated >>> below 4G in system address map. Otherwise the allocation fails on >>> platforms that do not have any memory below the 4G mark and the drive >>> initialisation fails. >>> >>> Cc: Ray Ni >>> Cc: Ard Biesheuvel >>> Cc: Leif Lindholm >>> Signed-off-by: Tomas Pilar >> NvmeControllerInit () can be called multiple times, no? So you should >> probably make sure that the buffer is not allocated and mapped again >> if one already exists. >> > Alternatively, you could move all PCI attribute handling into the > start() hook. Other drivers keep it there as well, and it seems like a > more natural place for it (given the fact that NvmeControllerInit() is > also called on a host controller reset) Brilliant idea, I'll do this!