From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.115; helo=mga14.intel.com; envelope-from=ruiyu.ni@intel.com; receiver=edk2-devel@lists.01.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 474EE21A07A80 for ; Tue, 25 Sep 2018 22:01:36 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Sep 2018 22:01:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,304,1534834800"; d="scan'208";a="76249252" Received: from ray-dev.ccr.corp.intel.com (HELO [10.239.9.8]) ([10.239.9.8]) by orsmga008.jf.intel.com with ESMTP; 25 Sep 2018 22:01:33 -0700 To: Eric Dong , edk2-devel@lists.01.org Cc: Michael D Kinney , Laszlo Ersek References: <20180925020853.25804-1-eric.dong@intel.com> From: "Ni, Ruiyu" Message-ID: <11525740-463a-3f4a-780e-287f141c1e3e@Intel.com> Date: Wed, 26 Sep 2018 13:02:30 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20180925020853.25804-1-eric.dong@intel.com> Subject: Re: [Patch v3 00/14] Update MSR definitions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Sep 2018 05:01:36 -0000 Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit On 9/25/2018 10:08 AM, Eric Dong wrote: > Current MSR definition are follow the SDM 2016-09 version. The latest SDM is 2018-05. This patch serial update the MSR related definition to follow the latest SDM 2018-05 version. MSR related defintion are saved at UefiCpuPkg\Include\Register\. > > V3 changes includes: > 1. Only change Patch 8 and 14 which changed MSR data structures. > 2. Keep ReservedX not change if bit info not changed for this field. > > V2 changes include: > 1. Only change Patch 8 and 14 which changed MSR data structures. > 2. Use X in ReservedX fields from totally new value if MSR structure definition changed. > For example, if in current structure, the max reserved variable is Reserved2, in new > definition, reserved variable is begin with Reserved3. > > V1 Changes include: > The changes for this serial includes: > 1. Add new MSR definition and file. > 2. Remove old MSR definition which not defined in new SDM. > 3. Change MSR name to follow new SDM, keep old one for compatibility. > 4. Change MSR data structure definition to follow new SDM. > 5. Update comments to follow the new SDM, mainly related to chapter info. > > Below changes are incompatible changes: > 2. Remove old MSR definition which not defined in new SDM. > For this one, i search edk2 codebase, not found any code uses it. so no impact for edk2 codebase. Detail changes see patch 9 ~ 11. > > 4. Change MSR data structure definition to follow new SDM. > For this one, new data structure just change the original reserved bits to valid bits, should have no impact for the current code. Detail see patch 8 and patch 14 > > Cc: Michael D Kinney > Cc: Ruiyu Ni > Cc: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Eric Dong > > > Eric Dong (14): > UefiCpuPkg/Include/Register/Msr: Update reference spec info. > UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h: Add new MSR file > for goldmont plus microarchitecture. > UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR. > UefiCpuPkg/Include/Register/Msr/*.h: Add new MSR. > UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR. > UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSRs. > UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Add new MSR. > UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure > definition. > UefiCpuPkg/Include/Register/Msr/Core2Msr.h: Remove old MSR. > UefiCpuPkg/Include/Register/Msr/P6Msr.h: Remove old MSR. > UefiCpuPkg/Include/Register/Msr/CoreMsr.h: Remove old MSR. > UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h: Add new MSR name and > keep old one. > UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h: Add new MSR name and > keep old one. > UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Change structure > definition. > > UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 130 +- > UefiCpuPkg/Include/Register/Msr.h | 7 +- > UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 28 +- > UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 62 +- > UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 102 +- > UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 74 +- > UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 88 +- > UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h | 272 ++++ > UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 62 +- > UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 34 +- > UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 8 +- > UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 52 +- > UefiCpuPkg/Include/Register/Msr/P6Msr.h | 60 +- > UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 202 +-- > UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 22 +- > UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 12 +- > UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 49 +- > UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 100 +- > UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1602 ++++++++++++++++++++- > UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 8 +- > UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 84 +- > UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 6 +- > UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 332 ++++- > 23 files changed, 2816 insertions(+), 580 deletions(-) > create mode 100644 UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h > Reviewed-by: Ruiyu Ni -- Thanks, Ray