From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web11.10632.1639400372217809539 for ; Mon, 13 Dec 2021 04:59:45 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@intel.com header.s=intel header.b=OeV0EUHJ; spf=pass (domain: intel.com, ip: 134.134.136.100, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1639400385; x=1670936385; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=WBKJPNCPIqsyyKlZLrQ75XtTEuzE7tIVOcWG1HPgL3Q=; b=OeV0EUHJPoj3bR0+j6C+ltO/YF68h+ZUJxbDvzuBzBxQMBf42uRDB1a7 sl0s8NFwT/Gx9kUsn0Xvhx+yuHnFENlUHrioNxodpjhQWjAUjz/hRut15 y1flhtgqPkqfpcFvC0Qe70tiU5Lx/ob0+RJrTEduKsca+8J65Ng6zmvbf ti6dNtRopjvpGQatupFQWopx6uXmlgJ8+4Y94DaXxN16Pvn2S7IJVAMKA FTuzuOdTg39GhXIQxp9GvPOubFvvmCLqtPwVNBEvT/Um0qzAxM4bQB1Xe g+Pj0QX//ogi7NV/rWNWDLDwAzNVtaH4E9ipBLADnPDMn+OBm0gjqdsGF Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10196"; a="302106134" X-IronPort-AV: E=Sophos;i="5.88,202,1635231600"; d="scan'208";a="302106134" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2021 04:59:45 -0800 X-IronPort-AV: E=Sophos;i="5.88,202,1635231600"; d="scan'208";a="517739079" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.173.142]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2021 04:59:42 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Jiewen Yao , Gerd Hoffmann , Anthony Perard , Julien Grall , Eric Dong , Ray Ni Subject: [PATCH V4 29/31] UefiCpuPkg: Setting initial-count register as the last step Date: Mon, 13 Dec 2021 20:57:00 +0800 Message-Id: <13c45431a42352de4088e8bd1edd527b6b0a4d30.1639399598.git.min.m.xu@intel.com> X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3711 Per SDM, changing the mode of APIC timer (from one-shot to periodic or vice versa) by writing to the timer LVT entry does not start the timer. To start the timer, it is necessary to write to the initial-count register. If initial-count is wrote before mode change, it's possible that timer expired before the mode change. Thus failing the periodic mode. Cc: Jiewen Yao Cc: Gerd Hoffmann Cc: Anthony Perard Cc: Julien Grall Cc: Eric Dong Cc: Ray Ni Signed-off-by: Min Xu --- .../Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index 2d17177df12b..f26d9c93894f 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -967,11 +967,6 @@ InitializeApicTimer ( // InitializeLocalApicSoftwareEnable (TRUE); - // - // Program init-count register. - // - WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount); - if (DivideValue != 0) { ASSERT (DivideValue <= 128); ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue)); @@ -996,6 +991,11 @@ InitializeApicTimer ( LvtTimer.Bits.Mask = 0; LvtTimer.Bits.Vector = Vector; WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32); + + // + // Program init-count register. + // + WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount); } /** -- 2.29.2.windows.2